SI5368B-C-GQ Silicon Laboratories Inc, SI5368B-C-GQ Datasheet - Page 37

• Manufacturer Part Number: SI5368B-C-GQ
• Description: IC CLK MULTIPLIER ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5368B-C-GQ

• Package / Case: 100-TQFP, 100-VQFP
• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Frequency-max: *
• Number Of Circuits: 1
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 0.002 MHz
• Output Frequency Range: 0.002 MHz to 808 MHz
• Supply Voltage (max): 2.75 V
• Supply Voltage (min): 1.71 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset value = 1101 1111
Register 22.
Name
Type
Bit
Bit
1
0
7
6
5
4
3
FSYNCOUT_
CK1_ACTV_
CKSEL_PIN
FSYNC_
CK_ACTV_
ALIGN_
Reserved
FSYNC_
FSYNC_
ALIGN_
POL
R/W
Name
D7
POL
POL
POL
POL
PIN
FSYNC_
CK1_ACTV_PIN.
The CK1_ACTV_REG status bit can be reflected to the CK1_ACTV output pin using the
CK1_ACTV_PIN enable function.
0: CK1_ACTV output pin tristated.
1: CK1_ACTV status reflected to output pin.
CKSEL_PIN.
If manual clock selection is being used, clock selection can be controlled via the
CKSEL_REG[1:0] register bits or the CKSEL[1:0] input pins.
0: CKSEL pins ignored. CKSEL_REG[1:0] register bits control clock selection.
1: CKSEL[1:0] input pins controls clock selection.
FSYNC_ALIGN_POL.
Sets the active polarity or edge for the FSYNC_ALIGN input pin.
0: Active low (falling edge).
1: Active high (rising edge).
FSYNC_POL.
Sets the active polarity and edge for the CKIN_3 and CKIN_4 inputs when used as frame
sync inputs.
0: Active low (falling edge).
1: Active high (rising edge).
Reserved.
FSYNCOUT_POL.
Controls active polarity of FSYNCOUT.
0: Active low
1: Active high
CK_ACTV_POL.
Sets the active polarity for the CK1_ACTV, CK2_ACTV, CK3_ACTV, and CK4_ACTV
signals when reflected on an output pin.
0: Active low
1: Active high
POL
R/W
D6
Reserved
D5
R
Preliminary Rev. 0.41
FSYNCOUT
_POL
R/W
D4
CK_ACTV_
Function
POL
R/W
D3
CK_BAD_
POL
R/W
D2
LOL_POL
R/W
D1
Si5368
INT_POL
R/W
D0
37