SI5368B-C-GQ Silicon Laboratories Inc, SI5368B-C-GQ Datasheet - Page 14

• Manufacturer Part Number: SI5368B-C-GQ
• Description: IC CLK MULTIPLIER ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5368B-C-GQ

• Package / Case: 100-TQFP, 100-VQFP
• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Frequency-max: *
• Number Of Circuits: 1
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 0.002 MHz
• Output Frequency Range: 0.002 MHz to 808 MHz
• Supply Voltage (max): 2.75 V
• Supply Voltage (min): 1.71 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5368
14
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
Pin #
55
58
59
60
61
68
69
70
SDA_SDO
Pin Name
A2_SS
C1A
C2A
SCL
INC
A0
A1
I/O
I/O
Table 3. Si5368 Pin Descriptions (Continued)
O
O
I
I
I
I
Signal Level
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Preliminary Rev. 0.41
Coarse Latency Increment.
A pulse on this pin increases the input to output device latency
by 1/fOSC (approximately 200 ps). Detailed operations, restric-
tions, and timing characteristics for this pin may be found in the
Any-Rate Precision Clock Family Reference Manual. There is
no limit on the range of latency adjustment by this method. Pin
control is enabled by setting INCDEC_PIN = 1 (default).
Note: INC does not increase latency if NI_HS = 4.
If INCDEC_PIN = 0, this pin is ignored and coarse output
latency is controlled via the CLAT register.
If both INC and DEC are tied high, phase buildout is disabled
and the device maintains a fixed-phase relationship between
the selected input clock and the output clock during an input
clock switch. Detailed operations and timing characteristics for
these pins may be found in the Any-Rate Precision Clock Fam-
ily Reference Manual.
This pin has a weak pull-down.
CKIN1 Active Clock Indicator.
This pin serves as the CKIN1 active clock indicator. The
CK1_ACTV_REG bit always reflects the active clock status for
CKIN1. If CK1_ACTV_PIN = 1, this status will also be reflected
on the C1A pin with active polarity controlled by the
CK_ACTV_POL bit. If CK1_ACTV_PIN = 0, this output tristates.
CKIN2 Active Clock Indicator.
This pin serves as the CKIN2 active clock indicator. The
CK2_ACTV_REG bit always reflects the active clock status for
CKIN_2. If CK2_ACTV_PIN = 1, this status will also be reflected
on the C2A pin with active polarity controlled by the
CK_ACTV_POL bit. If CK2_ACTV_PIN = 0, this output tristates.
Serial Clock.
This pin functions as the serial port clock input for both SPI and
I
This pin has a weak pull-down.
Serial Data.
In I
tions as the bidirectional serial data port. In SPI microprocessor
control mode (CMODE = 1), this pin functions as the serial data
output.
Serial Port Address.
In I
function as hardware controlled address bits. The I
is 1101 [A2] [A1] [A0]. In SPI microprocessor control mode
(CMODE = 1), these pins are ignored.
This pin has a weak pull-down.
Serial Port Address/Slave Select.
In I
tions as a hardware controlled address bit [A2].
In SPI microprocessor control mode (CMODE = 1), this pin
functions as the slave select input.
This pin has a weak pull-down.
2
C modes.
2
2
2
C microprocessor control mode (CMODE = 0), this pin func-
C microprocessor control mode (CMODE = 0), these pins
C microprocessor control mode (CMODE = 0), this pin func-
Description
2
C address