SI5368B-C-GQ Silicon Laboratories Inc, SI5368B-C-GQ Datasheet - Page 28

• Manufacturer Part Number: SI5368B-C-GQ
• Description: IC CLK MULTIPLIER ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5368B-C-GQ

• Package / Case: 100-TQFP, 100-VQFP
• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Frequency-max: *
• Number Of Circuits: 1
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 0.002 MHz
• Output Frequency Range: 0.002 MHz to 808 MHz
• Supply Voltage (max): 2.75 V
• Supply Voltage (min): 1.71 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5368
Reset value = 0000 0000
28
Register 10.
Name
Type
Bit
7:6
Bit
5
4
3
2
1
0
DSBL3_REG DSBL3_REG.
DSBL2_REG DSBL2_REG.
DSBL1_REG DSBL1_REG.
Reserved
Reserved
DSBL5_
DSBL4_
Name
D7
REG
REG
Reserved
R
Reserved.
DSBL5_REG.
This bit controls the powerdown and disable of the CKOUT5 output buffer. If disable
mode is selected, the NC5_LS output divider is also powered down.
0: CKOUT5 enabled.
1: CKOUT5 disabled.
Reserved.
DSBL4_REG.
This bit controls the powerdown and disable of the CKOUT4 output buffer. If disable
mode is selected, the NC4 output divider is also powered down.
0'b=CKOUT4 enabled
1'b=CKOUT4 disabled
This bit controls the powerdown and disable of the CKOUT3 output buffer. If disable
mode is selected, the NC3 output divider is also powered down.
0: CKOUT3 enabled
1: CKOUT3 disabled
This bit controls the powerdown and disable of the CKOUT2 output buffer. If disable
mode is selected, the NC2 output divider is also powered down.
0: CKOUT2 enabled
1: CKOUT2 disabled
This bit controls the powerdown and disable of the CKOUT1 output buffer. If disable
mode is selected, the NC1 output divider is also powered down.
0: CKOUT1 enabled
1: CKOUT1 disabled
D6
DSBL5_
REG
R/W
D5
Preliminary Rev. 0.41
Reserved
D4
R
DSBL4_
Function
REG
R/W
D3
DSBL3_
REG
R/W
D2
DSBL2_
REG
D1
R
DSBL1_
REG
D0
R