SI5315B-C-GMR Silicon Laboratories Inc, SI5315B-C-GMR Datasheet - Page 36

• Manufacturer Part Number: SI5315B-C-GMR
• Description: IC CLOCK MULT 8KHZ-125MHZ 36QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5315B-C-GMR

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 36-VQFN
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5315
4.6. PLL Bypass Mode
The Si5315 supports a PLL bypass mode in which the selected input clock is fed directly to both enabled output
buffers, bypassing the DSPLL. Internally, the bypass path is implemented with high-speed differential signaling;
however, this path is not a low jitter path and will see significantly higher jitter on CKOUT. In PLL bypass mode, the
input and output clocks will be at the same frequency. PLL bypass mode is useful in a laboratory environment to
measure system performance with and without the jitter attenuation provided by the DSPLL. The DSBL2_BY pin is
used to select the PLL Bypass Mode according to Table 14.
36
FRQSEL[3:0]
BWSEL[1:0]
AUTOSEL
FRQTBL
CS/CA
CKIN1+
CKIN1–
CKIN2+
CKIN2–
LOS1
LOS2
LOL
RST
2
2
Signal Detect
DSBL2/BYPASS
Bandwidth
Frequency
Control
Control
Control
M
H
L
Table 14. DSBL2/BYPASS Pin Settings
0
1
Xtal/Clock
f
3
Figure 9. Bypass Signal
XB
Reference Clock
PLL Bypass Mode w/ CKOUT2 Enabled
Crystal or
DSPLL
Rev. 0.26
®
CKOUT2 Disabled
CKOUT2 Enabled
XA
PLL Bypass
Function
f
OSC
0
0
1
1
2
2
VDD (1.8, 2.5, or 3.3 V)
GND
DBL2_BY
CKOUT1+
CKOUT1–
SFOUT[1:0]
CKOUT2+
CKOUT2–