ICS9248AG-92LFT IDT, Integrated Device Technology Inc, ICS9248AG-92LFT Datasheet - Page 7

IC PENTIUM II CLOCK CHIP 48TSSOP

ICS9248AG-92LFT

Manufacturer Part Number
ICS9248AG-92LFT
Description
IC PENTIUM II CLOCK CHIP 48TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Frequency Generatorr
Datasheet

Specifications of ICS9248AG-92LFT

Input
Crystal
Output
Clock
Frequency - Max
100MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Frequency-max
100MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
9248AG-92LFT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS9248AG-92LFT
Manufacturer:
ON
Quantity:
6 191
Power Management
Clock Enable Configuration
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power
up and power down operations using the PWR PD# select pin will not cause clocks of a short or longer pulse than that of the
running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network
charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9248-92 Power Management Requirements
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, SDRAM, PCICLK only.
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The REF will be stopped independant of these.
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