ICS9248DF-39LF IDT, Integrated Device Technology Inc, ICS9248DF-39LF Datasheet - Page 12

IC GEN/BUFFER PENTIUM PRO 48SSOP

ICS9248DF-39LF

Manufacturer Part Number
ICS9248DF-39LF
Description
IC GEN/BUFFER PENTIUM PRO 48SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Frequency Generatorr
Datasheet

Specifications of ICS9248DF-39LF

Input
Crystal
Output
Clock
Frequency - Max
150MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-SSOP
Frequency-max
150MHz
Number Of Elements
2
Supply Current
180mA
Pll Input Freq (min)
12MHz
Pll Input Freq (max)
16MHz
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
SSOP
Output Frequency Range
24 to 150MHz
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Commercial
Pin Count
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
9248DF-39LF

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0
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation. CPU_STOP# is synchronized by the ICS9248-39. The minimum that the CPU clock is enabled (CPU_STOP#
high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
0277G—08/04/04
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
3. IOAPIC output is Stopped Glitch Free by CPUSTOP# going low.
4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-39
5. All other clocks continue to run undisturbed.
ICS9248-39
synchronized to the CPU clocks inside the ICS9248-39.
CPU_STOP# signal. SDRAM (0:11) are controlled as shown.
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