SAF82526NV2.2XT Infineon Technologies, SAF82526NV2.2XT Datasheet - Page 23

• Manufacturer Part Number: SAF82526NV2.2XT
• Manufacturer: Infineon Technologies

Specifications of SAF82526NV2.2XT

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

Beside those bit-oriented functions usually supported with the HDLC protocol, such as bit
stuffing, CRC check, flag and address recognition, the HSCX provides a high degree of
procedural support. In a special operating mode (auto-mode), the HSCX processes the
information transfer and the procedure handshaking (I-, and S-frames of HDLC protocol)
autonomously. The only restriction is, that the window size (= number of outstanding
unacknowledged frames) is limited to 1, which will be sufficient in most applications. The
communication procedures are mainly processed between the communication controllers and
not between the processors. Thus the dynamic load of the CPU and the software expense is
largely reduced.
Figure 7
Procedural Support in Auto-Mode
The CPU is informed about the status of the procedure and has to manage the receive and
transmit data mainly. In order to maintain cost effectiveness and flexibility, such functions as
link setup/disconnection and error recovery in case of protocol errors (U-frames of HDLC
protocols) are not implemented in hardware and must be done by user’s software.
In a special operating mode, the HSCX can transmit or receive data packets in one of up to 64
time-slots of programmable width (clock mode 5). Furthermore, the HSCX can transmit or
receive variable data portions within a defined window of one or more clock cycles, which has
to be selected by an external strobe signal (clock mode 1). These features make the HSCX
especially suitable for all applications using time division multiplex methods, such as time-slot
oriented PCM systems, systems designed for packet switching, or in ISDN applications.
A further speciality of HSCX are the FIFO buffers used for the temporary storage of data
packets transferred between the serial communications interface and the parallel system bus.
Also because of the overlapping input/output operation (dual-port behaviour), the maximum
message length is not limited by the size of the buffer. Together with the DMA capability, the
dynamic load of the CPU is drastically reduced by transferring the data packets block by block
via direct memory access. The CPU only has to initiate the data transmission by the HSCX and
determine the status in case of completely received frames, but is not involved in data
transfers.
Semiconductor Group
Support of layer-2 functions by HSCX
Telecom specific features
FIFO buffers to efficient transfer of data packets.
P µ
HSCX
S Frame
U
I
Frame
Frame
23
HSCX
µP
ITS05502
SAB
SAB
SAF
SAF
82525
82526
82525
82526