STM32L-DISCOVERY STMicroelectronics, STM32L-DISCOVERY Datasheet - Page 122

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STM32L-DISCOVERY

Manufacturer Part Number
STM32L-DISCOVERY
Description
BOARD, EVAL, STM32L-DISCOVERY
Manufacturer
STMicroelectronics
Series
STM32r
Type
MCUr
Datasheets

Specifications of STM32L-DISCOVERY

Kit Contents
Board, Debugger, Programmer And Compiler
Features
128KB Flash Plus Multiple Timers, Analogue Peripherals
Silicon Manufacturer
ST Micro
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
STM32
Silicon Family Name
STM32F1xx
Rohs Compliant
Yes
Contents
Board
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
STM32L
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STM32L-DISCOVERY
Manufacturer:
STMicroelectronics
Quantity:
18
Part Number:
STM32L-DISCOVERY
Manufacturer:
ST
0
Electrical characteristics
122/163
Figure 57. Asynchronous multiplexed PSRAM/NOR write waveforms
Table 70.
1. C
2. Preliminary values.
t
t
t
t
t
t
t
t
t
t
t
t
t
w(NE)
v(NWE_NE)
w(NWE)
h(NE_NWE)
v(A_NE)
v(NADV_NE)
w(NADV)
h(AD_NADV)
h(A_NWE)
v(BL_NE)
h(BL_NWE)
v(Data_NADV)
h(Data_NWE)
Symbol
L
= 15 pF.
FSMC_NBL[1:0]
FSMC_ AD[15:0]
FSMC_A[25:16]
FSMC_NADV
FSMC_NWE
FSMC_NOE
FSMC_NEx
Asynchronous multiplexed PSRAM/NOR write timings
FSMC_NE low time
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
FSMC_AD (address) valid hold time after
FSMC_NADV high
Address hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NWE high
FSMC_NADV high to Data valid
Data hold time after FSMC_NWE high
Doc ID 15818 Rev 6
Parameter
t
v(NADV_NE)
t
t
t
v(A_NE)
v(A_NE)
t
t
v(NWE_NE)
v(BL_NE)
w(NADV)
Address
Address
t
t
t
v(Data_NADV)
w(NE)
h(AD_NADV)
NBL
t
w(NWE)
t
h(BL_NWE)
t
h(A_NWE)
Data
5T
2T
2T
T
3
T
T
4T
T
T
STM32F205xx, STM32F207xx
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
Min
– 1
– 1
– 3
– 1.5
– 5
– 1
– 1
(1)(2)
t
5T
2T
2T
7
5
T
1.6
T
h(Data_NWE)
t
HCLK
HCLK
h(NE_NWE)
HCLK
HCLK
HCLK
Max
+ 1
+ 1.5
+ 2
+ 1
+ 2
ai14891B
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit

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