STM32L-DISCOVERY STMicroelectronics, STM32L-DISCOVERY Datasheet - Page 100

• Manufacturer Part Number: STM32L-DISCOVERY
• Description: BOARD, EVAL, STM32L-DISCOVERY
• Manufacturer: STMicroelectronics
• Series: STM32r
• Type: MCUr

Specifications of STM32L-DISCOVERY

• Kit Contents: Board, Debugger, Programmer And Compiler
• Features: 128KB Flash Plus Multiple Timers, Analogue Peripherals
• Silicon Manufacturer: ST Micro
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: STM32
• Silicon Family Name: STM32F1xx
• Rohs Compliant: Yes
• Contents: Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: STM32L
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical characteristics
100/163
I
Unless otherwise specified, the parameters given in
are derived from tests performed under the ambient temperature, f
supply voltage conditions summarized in
Refer to
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I
Table 49.
1. Remapped SPI1 characteristics to be determined.
2. TBD stands for “to be defined”.
3. Based on characterization, not tested in production.
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
2
DuCy(SCK)
t
t
t
dis(SO)
t
S - SPI interface characteristics
t
t
t
w(SCLH)
v(SO)
t
w(SCLL)
a(SO)
v(MO)
1/t
su(NSS)
t
Symbol
t
h(NSS)
t
t
t
su(MI)
t
h(MO)
the data.
the data in Hi-Z
su(SI)
h(MI)
h(SO)
t
t
h(SI)
r(SCL)
f
f(SCL)
c(SCK)
SCK
(3)(4)
(3)(1)
(3)(1)
(3)
(3)(5)
(3)
(3)
(3)
(3)
(3)
(3)
Section 5.3.16: I/O port characteristics
(3)
(3)
(3)
SPI characteristics
SPI clock frequency
SPI clock rise and fall
time
SPI slave input clock
duty cycle
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access
time
Data output disable
time
Data output valid time Slave mode (after enable edge)
Data output valid time Master mode (after enable edge)
Data output hold time
Parameter
Doc ID 15818 Rev 6
(1)(2)
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Slave mode
Master mode, f
presc = 4
Master mode
Slave mode
Master mode
Slave mode
Slave mode, f
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Table
Conditions
10.
for more details on the input/output alternate
PCLK
PCLK
= 20 MHz
Table 49
= 30 MHz,
STM32F205xx, STM32F207xx
for SPI or in
PCLKx
4 t
2 t
TBD
Min
30
PCLK
PCLK
15
5
5
5
4
2
2
-
-
-
-
-
0
frequency and V
Table 50
3 t
TBD
Max
30
70
10
25
2
PCLK
30
-
-
-
8
-
-
-
-
5
-
S).
for I
MHz
Unit
ns
ns
%
2
S
DD