HW-FMC-XM105-G Xilinx Inc, HW-FMC-XM105-G Datasheet - Page 10
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HW-FMC-XM105-G
Manufacturer Part Number
HW-FMC-XM105-G
Description
CARD, CONNECTIVITY, FMC XM105
Manufacturer
Xilinx Inc
Datasheet
1.HW-FMC-XM105-G.pdf
(30 pages)
Specifications of HW-FMC-XM105-G
Kit Contents
FMC XM105 Debug Card, Welcome Letter, 4x Mounting Screws, 2x Standoffs
Features
VITA 57.1 FMC HPC Connector, Power Good LEDs
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 1: XM105
Board Technical Description
10
The XM105 provides a number of multi-position headers and connectors which break out
the FPGA interface signals to and from the board interface. A serial IIC bus
reprogrammable LVDS clock source and a pair of SMA connectors provide differential
clock sources to the board FGPA. A 2-Kb serial IIC EEPROM is connected to the IIC
interface of the board providing non-volatile storage.
Figure 1-2
when the board interface is a high pin count board interface. All other interfaces are
available for low pin count board applications.
X-Ref Target - Figure 1-2
SMA J9, J10
J23 Header
LVDS Clock
FMC JTAG
J2 Header
J3 Header
J5 Header
EEPROM
2 x 20
2 x 20
shows a block diagram of the XM105. The gray shaded blocks are only available
2 x 6
1 x 9
2 Kb
Requires board with FMC HPC support.
www.xilinx.com
Figure 1-2: XM105 Block Diagram
FMC HPC
Interface
J17
Power Good
J20 Header
J16 Header
J15 Header
38 Position
J1 Header
Mictor P1
2 x 20
LEDs
2 x 8
2 x 6
1 x 6
FMC XM105 Debug Card User Guide
UG537 (v1.2) September 24, 2010
1 x 9 JTAG
J19 Head
UG537_02_110509
LEDs
User