LFEC10E-3F484C LATTICE SEMICONDUCTOR, LFEC10E-3F484C Datasheet - Page 60

• Manufacturer Part Number: LFEC10E-3F484C
• Description: FPGA LatticeEC Family 10200 Cells 340MHz 130nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFEC10E-3F484C

• Package: 484FBGA
• Family Name: LatticeEC
• Device Logic Units: 10200
• Maximum Internal Frequency: 340 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 288
• Ram Bits: 282624
• In System Programmability: Yes

Lattice Semiconductor
LatticeECP/EC sysCONFIG Port Timing Specifications
sysCONFIG Byte Data Flow
t
t
t
t
t
t
t
t
t
sysCONFIG Byte Slave Clocking
t
t
t
t
t
t
sysCONFIG Serial (Bit) Data Flow
t
t
sysCONFIG Serial Slave Clocking
t
t
sysCONFIG POR, Initialization and Wake Up
t
t
t
t
t
t
t
t
t
t
t
t
sysCONFIG SPI Port
t
t
t
t
SUCBDI
HCBDI
CODO
SUCS
HCS
SUWD
HWD
DCB
CORD
BSCH
BSCL
BSCYC
SUSCDI
HSCDI
CODO
SUMCDI
HMCDI
SSCH
SSCL
ICFG
VMC
PRGMRJ
PRGM
DINIT
DPPINIT
DINITD
IODISS
IOENSS
MWC
SUCFG
HCFG
CFGX
CSSPI
CSCCLK
SOCDO
Parameter
Byte D[0:7] Setup Time to CCLK
Byte D[0:7] Hold Time to CCLK
Clock to Dout in Flowthrough Mode
CS[0:1] Setup Time to CCLK
CS[0:1] Hold Time to CCLK
Write Signal Setup Time to CCLK
Write Signal Hold Time to CCLK
CCLK to BUSY Delay Time
Clock to Out for Read Data
Byte Slave Clock Minimum High Pulse
Byte Slave Clock Minimum Low Pulse
Byte Slave Clock Cycle Time
Din Setup time to CCLK Slave Mode
Din Hold Time to CCLK Slave Mode
Clock to Dout in Flowthrough Mode
Din Setup time to CCLK Master Mode
Din Hold Time to CCLK Master Mode
Serial Slave Clock Minimum High Pulse
Serial Slave Clock Minimum Low Pulse
Minimum Vcc to INIT High
Time from tICFG to Valid Master Clock
Program Pin Pulse Rejection
PROGRAMN Low Time to Start Configuration
INIT Low Time
Delay Time from PROGRAMN Low to INIT Low
Delay Time from PROGRAMN Low to DONE Low
User I/O Disable from PROGRAMN Low
User I/O Enabled Time from CCLK Edge During Wake Up
Sequence
Additional Wake Master Clock Signals after Done Pin High
CFG to INITN Setup Time
CFG to INITN Hold Time
Init High to CCLK Low
Init High to CSSPIN Low
CCLK Low Before CSSPIN Low
CCLK Low to Output Valid
Over Recommended Operating Conditions
Description
3-24
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Min.
100
100
120
15
25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7
1
7
1
7
1
6
9
7
1
7
1
6
6
0
Typ.
Max.
12
12
12
12
50
37
37
35
25
80
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
8
1
2
-
cycles
Units
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns