SI5317C-C-GMR Silicon Laboratories Inc, SI5317C-C-GMR Datasheet - Page 39

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SI5317C-C-GMR

Manufacturer Part Number
SI5317C-C-GMR
Description
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI5317C-C-GMR

Lead Free Status / RoHS Status
Supplier Unconfirmed
Pin #
23
22
27
26
25
24
29
28
33
30
34
35
CKOUT1–
CKOUT1+
CKOUT2–
CKOUT2+
Pin Name
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
BWSEL1
BWSEL0
SFOUT0
SFOUT1
Table 15. Si5317 Pin Descriptions (Continued)
I/O
O
O
I
I
Signal Level
3-Level
3-Level
Multi
Multi
Loop Bandwidth Select.
Three level inputs that select the DSPLL closed loop band-
width. See Table 9 on page 22 for available settings.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Frequency Select.
Three level inputs that select the input clock and clock range.
See Table 9 on page 22.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Clock Output 1.
Output signal format is selected by SFOUT pins. Differential
formats supported for LVPECL, LVDS, and CML compatible
modes. For single-ended CMOS format, both output pins
drive identical, in-phase clock outputs.
Signal Format Select.
Three-level inputs that select the output signal format (com-
mon mode voltage and differential swing) for both CKOUT1
and CKOUT2.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.*
CMOS outputs do not support bypass mode.
Clock Output 2.
Output signal format is selected by SFOUT pins. Differential
formats supported for LVPECL, LVDS, and CML compatible
modes. For single-ended CMOS format, both output pins
drive identical, in-phase clock outputs.
Rev. 1.0
SFOUT[1:0]
MM
HM
MH
HH
ML
LM
HL
LH
LL
Description
Reserved
LVDS
CML
LVPECL
Reserved
LVDS—Low Swing
CMOS
Disable
Reserved
Signal Format
Si5317
39

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