ADSP-BF592KCPZ Analog Devices Inc, ADSP-BF592KCPZ Datasheet - Page 7

• Manufacturer Part Number: ADSP-BF592KCPZ
• Description: 58T4522
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF592KCPZ

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Rohs Compliant: YES
• Frequency: 400MHz
• Embedded Interface Type: PPI, SPI, UART
• No. Of I/o's: 32
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Core Supply Voltage: 1.4V
• Lead Free Status / RoHS Status: Compliant

Preliminary Technical Data
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
Table 3. System Interrupt Controller (SIC)
Peripheral Interrupt Source
PLL Wakeup Interrupt
DMA Error (generic)
PPI0 Status
SPORT0 Status
SPORT1 Status
SPI0 Status
SPI1 Status
UART0 Status
DMA Channel 0 (PPI0)
DMA Channel 1 (SPORT0 RX)
DMA Channel 2 (SPORT0 TX)
DMA Channel 3 (SPORT1 RX)
DMA Channel 4 (SPORT1 TX)
DMA Channel 5 (SPI0 RX/TX)
DMA Channel 6 (SPI1 RX/TX)
DMA Channel 7 (UART0 RX)
DMA Channel 8 (UART0 TX)
Port F Interrupt A
Port F Interrupt B
Timer 0
Timer 1
Timer 2
Port G Interrupt A
Port G Interrupt B
TWI
Reserved
Reserved
Reserved
Reserved
DMA Channels 12 and 13 (Memory DMA Stream 0)
DMA Channels 14 and 15 (Memory DMA Stream 1)
Software Watchdog Timer
• SIC interrupt wakeup enable registers (SIC_IWR) – By
source triggered the interrupt. A set bit indicates that the
peripheral is asserting the interrupt, and a cleared bit indi-
cates that the peripheral is not asserting the event.
enabling the corresponding bit in these registers, a periph-
eral can be configured to wake up the processor, should the
core be idled or in sleep mode when the event is generated.
For more information, see
on Page
10.
Dynamic Power Management
Rev. PrC | Page 7 of 46 | August 2010
Interrupt (at Reset)
General Purpose
IVG10
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG11
IVG11
IVG12
IVG12
IVG12
IVG13
IVG13
IVG13
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG8
IVG9
IVG9
IVG9
IVG9
–
–
–
–
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC recognizes and queues the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.
Interrupt ID
Peripheral
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
1
2
3
4
5
6
7
8
9
Default Core
Interrupt ID
0
0
0
0
0
0
0
0
1
2
2
2
2
3
3
3
3
4
4
4
4
4
5
5
5
–
–
–
–
6
6
6
ADSP-BF592
SIC Interrupt
Assignment
IAR0
IAR0
IAR0
IAR0
IAR0
IAR0
IAR0
IAR0
IAR1
IAR1
IAR1
IAR1
IAR1
IAR1
IAR1
IAR1
IAR2
IAR2
IAR2
IAR2
IAR2
IAR2
IAR2
IAR2
IAR3
IAR3
IAR3
IAR3
IAR3
IAR3
IAR3
IAR3