ADSP-BF592KCPZ Analog Devices Inc, ADSP-BF592KCPZ Datasheet - Page 39

58T4522

ADSP-BF592KCPZ

Manufacturer Part Number
ADSP-BF592KCPZ
Description
58T4522
Manufacturer
Analog Devices Inc
Datasheets

Specifications of ADSP-BF592KCPZ

Operating Temperature (min)
0C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Rohs Compliant
YES
Frequency
400MHz
Embedded Interface Type
PPI, SPI, UART
No. Of I/o's
32
Operating Temperature Range
0°C To +70°C
Digital Ic Case Style
LFCSP
No. Of Pins
64
Core Supply Voltage
1.4V
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-BF592KCPZ-2
Manufacturer:
BROADCOM
Quantity:
154
Preliminary Technical Data
The time t
signal switches, to when the output voltage reaches V
or V
1.05V, and V
V
nal) = 3.3V, V
t
the output reaches the V
Time t
If multiple pins are enabled, the measurement value is that of
the first lead to start driving.
Output Disable Time Measurement
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time t
difference between t
side of
The time for the voltage on the bus to decay by ΔV is dependent
on the capacitive load C
time can be approximated by the equation:
The time t
ΔV equal to 0.25 V for V
V for V
The time t
signal switches, to when the output voltage decays ΔV from the
measured output high or output low voltage.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. C
the total bus capacitance (per data line), and I
age or three-state current (per data line). The hold time will be
t
Timing Specifications on Page
TRIP
DECAY
TRIP
TRIP
is the interval from when the output starts driving to when
(high) is 1.5V and V
plus the various output disable times as specified in the
ENA
Figure
DDEXT
(low). For V
ENA_MEASURED
is calculated as shown in the equation:
DECAY
DIS_MEASURED
TRIP
(nominal) = 1.8V.
TRIP
34.
DECAY
t
is calculated with test loads C
DIS
(low) is 0.75V. For V
t
(high) is 1.9V, and V
ENA
DDEXT
DIS_MEASURED
using the equation given above. Choose ΔV
=
t
DECAY
is the interval from when the reference
is the interval, from when the reference
t
=
DIS_MEASURED
L
TRIP
DDEXT
and the load current I
(nominal) = 1.8V, V
TRIP
t
ENA_MEASURED
(high) or V
=
(low) is 1.0V. For V
(nominal) = 2.5 V/3.3 V and 0.15
23.
(
and t
C
L
Δ
V
DECAY
t
DDEXT
) I
DECAY
TRIP
TRIP
t
L
TRIP
(low) trip voltage.
(low) is 1.4V. Time
as shown on the left
(nominal) = 2.5V,
L
L
TRIP
and I
is the total leak-
L
. This decay
DDEXT
(high) is
Rev. PrC | Page 39 of 46 | August 2010
L
, and with
DIS
TRIP
(nomi-
is the
(high)
L
is
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see
to (V
The graphs of
rise time varies with capacitance. The delay and hold specifica-
tions given should be derated by a factor derived from these
figures. The graphs in these figures may not be linear outside the
ranges shown.
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
V
LOAD
4pF
20
18
16
14
12
10
Figure 36. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
8
6
4
2
0
DDEXT
0
Figure 35. Equivalent Device Loading for AC Measurements
50:
) /2.
Figure 39
70:
50:
400:
2pF
50
Load Capacitance (1.8V V
TESTER PIN ELECTRONICS
through
(Includes All Fixtures)
LOAD CAPACITANCE (pF)
45:
0.5pF
100
Figure 38
Figure
ZO = 50: (impedance)
TD = 4.04 r 1.18 ns
150
DDEXT
show how output
ADSP-BF592
T1
t
35). V
FALL
)
t
t
FALL
RISE
= 1.8V @ 25
= 1.8V @ 25
t
RISE
LOAD
200
is equal
OUTPUT
DUT
° C
° C
250

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