ADSP-BF592KCPZ Analog Devices Inc, ADSP-BF592KCPZ Datasheet - Page 25

• Manufacturer Part Number: ADSP-BF592KCPZ
• Description: 58T4522
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF592KCPZ

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Rohs Compliant: YES
• Frequency: 400MHz
• Embedded Interface Type: PPI, SPI, UART
• No. Of I/o's: 32
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Core Supply Voltage: 1.4V
• Lead Free Status / RoHS Status: Compliant

Preliminary Technical Data
Parallel Peripheral Interface Timing
Table 22
Figure 15 on Page 29
operations.
Table 22. Parallel Peripheral Interface Timing
1
Parameter
Timing Requirements
t
t
Timing Requirements - GP Input and Frame Capture Modes
t
t
t
t
Switching Characteristics - GP Output and Frame Capture Modes
t
t
t
t
PPI_CLK frequency cannot exceed f
PCLKW
PCLK
SFSPE
HFSPE
SDRPE
HDRPE
DFSPE
HOFSPE
DDTPE
HDTPE
and
Figure 9 on Page
PPI_CLK Width
PPI_CLK Period
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
PPI_FS1/2
PPI_DATA
PPI_CLK
describe parallel peripheral interface
1
SCLK
1
t
SFSPE
25,
/2
Figure 13 on Page
FRAME SYNC SAMPLED
DATA SAMPLED /
Figure 9. PPI GP Rx Mode with External Frame Sync Timing
Rev. PrC | Page 25 of 46 | August 2010
28, and
t
HFSPE
t
SDRPE
FRAME SYNC SAMPLED
DATA SAMPLED /
t
PCLKW
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
1.8V Nominal
t
HDRPE
V
DDEXT
t
PCLK
Max
TBD
TBD
2.5/3.3V Nominal
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
V
DDEXT
ADSP-BF592
Max
TBD
TBD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns