CY7C4281V-10JC Cypress Semiconductor Corp, CY7C4281V-10JC Datasheet - Page 5

• Manufacturer Part Number: CY7C4281V-10JC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4281V-10JC

• Configuration: Dual
• Density: 576Kb
• Access Time (max): 8ns
• Word Size: 9b
• Organization: 64Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PLCC
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 25mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-06013 Rev. *B
Table 2. Status Flags
Width-Expansion Configuration
Word width may be increased simply by connecting the corre-
sponding input controls signals of multiple devices. A
composite flag should be created for each of the end-point
status flags (EF and FF). The partial status flags (PAE and
PAF) can be detected from any one device. Figure 2 demon-
strates a 18-bit word width by using two CY7C42x1Vs. Any
word width can be attained by adding additional CY7C42x1Vs.
When the CY7C42x1V is in a Width-Expansion Configuration,
the Read Enable (REN2) control input can be grounded (see
Figure 2). In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Notes:
0
1 to n
(n + 1) to (1638 − (m + 1)) (n + 1) to (32768 − (m + 1)) (n + 1) to (65536 − (m + 1)) (n + 1) to (131072 −
(16384 − m)
16384
WRITE ENABLE 1(WEN1)
2. n = Empty Offset (n = 7 default value).
3. m = Full Offset (m = 7 default value).
WRITE ENABLE 2/LOAD
PROGRAMMABLE(PAF)
DATA IN (D)
WRITECLOCK (WCLK)
[2]
CY7C4261V
FULL FLAG (FF) # 1
FULL FLAG (FF) # 2
[3]
to 16383 (32768 − m)
(WEN2/LD)
18
Figure 2. Block Diagram of 16k/32k/64k/128k x 9 Low-Voltage Deep Sync FIFO Memory
9
0
1 to n
32768
Read Enable 2 (REN2)
FF
[2]
CY7C4261V
CY7C4271V
CY7C4281V
CY7C4291V
CY7C4271V
RESET (RS)
[3]
Number of Words in FIFO
to 32767
Used in a Width-Expansion Configuration
EF
9
0
1 to n
(65536 − m)
65536
[2]
CY7C4281V
9
[3]
Flag Operation
The CY7C4261/71/81/91V devices provide five flag pins to
indicate the condition of the FIFO contents. Empty, Full, PAE,
and PAF are synchronous.
Full Flag
The Full Flag (FF) will go LOW when the device is full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN1 and WEN2/LD. FF is synchronized to WCLK,
i.e., it is exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN1 and REN2. EF is synchronized
to RCLK, i.e., it is exclusively updated by each rising edge of
RCLK.
Read Enable 2 (REN2)
to 65535
FF
CY7C4261V
CY7C4271V
CY7C4281V
CY7C4291V
RESET (RS)
0
1 to n
(m + 1))
(131072 − m)
131072
EF
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
[2]
CY7C4291V
EMPTY FLAG (EF) #2
EMPTY FLAG (EF) #1
9
READ CLOCK (RCLK)
READ ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
PROGRAMMABLE(PAE)
[3]
to 131071 H
DATA OUT (Q)
FF PAF PAE EF
H
H
H
L
H
H
H
L
L
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