CY7C4281V-10JC Cypress Semiconductor Corp, CY7C4281V-10JC Datasheet - Page 13

• Manufacturer Part Number: CY7C4281V-10JC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4281V-10JC

• Configuration: Dual
• Density: 576Kb
• Access Time (max): 8ns
• Word Size: 9b
• Organization: 64Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PLCC
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 25mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-06013 Rev. *B
Switching Waveforms
Programmable Almost Full Flag Timing
Write Programmable Registers
Notes:
22. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW.
23. PAF offset = m.
24. 16K − m words for CY7C4261V, 32K – m words for CY7C4271V, 64K − m words for CY7C4281V, and 128K − m words for CY4291V.
25. t
WEN2/LD
of RCLK and the rising edge of WCLK is less than t
SKEW2
(if applicable)
WCLK
WEN1
D
0
WEN2
–D
WCLK
WEN1
REN1,
is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge
RCLK
REN2
PAF
8
t
CLKH
t
CLKH
(continued)
FULL − (M+1)WORDS
t
CLK
t
t
ENS
ENS
t
DS
IN FIFO
PAE OFFSET
t
t
ENS
ENS
LSB
SKEW2
t
t
ENH
ENH
t
CLKL
t
, then PAF may not change state until the next WCLK.
CLKL
t
ENH
t
DH
Note
PAE OFFSET
Note
MSB
22
23
t
PAF
t
ENS
PAF OFFSET
t
SKEW2
(FULL −M) WORDS
LSB
IN FIFO
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
t
ENS
[25]
t
[24]
ENH
PAF OFFSET
MSB
t
PAF
Page 13 of 16
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