MT48H32M16LFCJ-8:A Micron Technology Inc, MT48H32M16LFCJ-8:A Datasheet - Page 6

• Manufacturer Part Number: MT48H32M16LFCJ-8:A
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48H32M16LFCJ-8:A

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 9/7ns
• Maximum Clock Rate: 125MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 85mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Functional Block Diagrams
Figure 2:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
BA0, BA1
A0–A12,
CAS#
RAS#
WE#
CKE
CLK
CS#
15
32 Meg x 16 SDRAM
ADDRESS
REGISTER
MODE REGISTER
EXT MODE
REGISTER
CONTROL
LOGIC
13
The 512Mb SDRAM is designed to operate in 1.8V low-power memory systems. An auto
refresh mode is provided, along with a power-saving deep power-down mode. All inputs
and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks in order to hide precharge
time, and the capability to randomly change column addresses on each clock cycle
during a burst access.
COUNTER
REFRESH
13
10
2
13
ADDRESS
2
ROW-
MUX
COUNTER/
CONTROL
COLUMN-
ADDRESS
LATCH
LOGIC
BANK
13
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
ADDRESS
DECODER
BANK0
LATCH
ROW-
AND
10
6
8,192
READ DATA LATCH
(8,192 x 1,024 x 16)
SENSE AMPLIFIERS
DQM MASK LOGIC
WRITE DRIVERS
I/O GATING
DECODER
COLUMN
MEMORY
BANK0
ARRAY
16,384
1,024
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(x16)
BANK1
BANK2
BANK3
BA1
0
0
1
1
Functional Block Diagrams
16
16
2
BA0
0
1
0
1
REGISTER
REGISTER
OUTPUT
©2005 Micron Technology, Inc. All rights reserved.
DATA
DATA
INPUT
Bank
0
1
2
3
2
16
DQML,
DQMH
DQ0–
DQ15