MT48H32M16LFCJ-8:A Micron Technology Inc, MT48H32M16LFCJ-8:A Datasheet - Page 30

• Manufacturer Part Number: MT48H32M16LFCJ-8:A
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48H32M16LFCJ-8:A

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 9/7ns
• Maximum Clock Rate: 125MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 85mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

WRITEs
Figure 18:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
WRITE Command
Notes:
WRITE bursts are initiated with a WRITE command, as shown in Figure 18.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other
commands have been initiated, the DQs will remain High-Z and any additional input
data will be ignored (see Figure 19 on page 31).
A9, A11, A12
1. EN AP = enable auto precharge
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 20 on page 31. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. The 512Mb SDRAM uses a pipe-
lined architecture and therefore does not require the 2n rule associated with a prefetch
architecture. A WRITE command can be initiated on any clock cycle following a previous
BA0, BA1
DIS AP = disable auto precharge
A0–A8
RAS#
CAS#
A10
WE#
CKE
CLK
CS#
1
HIGH
VALID ADDRESS
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
ADDRESS
ADDRESS
COLUMN
DIS AP
EN AP
BANK
30
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©2005 Micron Technology, Inc. All rights reserved.
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