LTM9005IV-AB#PBF Linear Technology, LTM9005IV-AB#PBF Datasheet - Page 13

• Manufacturer Part Number: LTM9005IV-AB#PBF
• Manufacturer: Linear Technology

Specifications of LTM9005IV-AB#PBF

• Lead Free Status / RoHS Status: Compliant

operaTion
Down-Converting Mixer
The mixer stage consists of a high linearity double-bal-
anced mixer, RF buffer amplifier, high speed limiting LO
buffer amplifier and bias/enable circuits. The RF and LO
inputs are both single ended. Low side or high side LO
injection can be used.
The RF input consists of an integrated transformer and a
high linearity differential amplifier. The primary terminals of
the transformer are connected to the RF input and ground.
The secondary side of the transformer is internally con-
nected to the amplifier’s differential inputs.
The LO input consists of an integrated transformer and
high speed limiting differential amplifiers. The amplifiers
are designed to precisely drive the mixer for the highest
linearity and the lowest noise figure.
Attenuator
A dual PIN diode with common-cathode connection is
used for continuously variable attenuation. The anodes
are connected to the outputs of the mixer and pulled up
to V
series 50Ω resistor to GAIN. See the GAIN Control Input
section for applications information.
First and Second Amplifiers
The amplifiers used in the LTM9005 are low noise and
low distortion fully differential ADC drivers. The ampli-
fiers are fully differential amplifiers with on chip feedback
resistors.
SAW Filter
A high selectivity, surface acoustic wave (SAW) filter is
integrated in the LTM9005.
(Applications to provide additional text)
Band-Pass Filter
An L-C bandpass filter follows the second amplifier to
prevent aliasing and to minimize the noise contribution
of the second amplifier.
(Applications to provide additional text)
CC1
through 100nH inductors. The cathode includes a
Analog to Digital Converter
The analog-to-digital converter (ADC) is a CMOS pipelined
multistep converter. The converter has six pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later (see Digital Output Bus Timing). The
CLK input is single-ended. The ADC has two phases of
operation, determined by the state of the CLK input pin.
Each pipelined stage contains an ADC, a reconstruction
DAC and an interstage residue amplifier. In operation, the
ADC quantizes the input to the stage and the quantized
value is subtracted from the input by the DAC to produce a
residue. The residue is amplified and output by the residue
amplifier. Successive stages operate out of phase so that
when the odd stages are outputting their residue, the even
stages are acquiring that residue and visa versa.
When CLK is low, the analog input is sampled differen-
tially directly onto the input sample-and-hold capacitors.
At the instant that CLK transitions from low to high, the
sampled input is held. While CLK is high, the held input
voltage is buffered by the S/H amplifier which drives the
first pipelined ADC stage. The first stage acquires the
output of the S/H during this high phase of CLK. When
CLK goes back low, the first stage produces its residue
which is acquired by the second stage. At the same time,
the input S/H goes back to acquiring the analog input.
When CLK goes back high, the second stage produces its
residue which is acquired by the third stage. An identical
process is repeated for the third, fourth and fifth stages,
resulting in a fifth stage residue that is sent to the sixth
stage ADC for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
LTM9005
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9005p