LTM9005IV-AA#PBF Linear Technology, LTM9005IV-AA#PBF Datasheet

no-image

LTM9005IV-AA#PBF

Manufacturer Part Number
LTM9005IV-AA#PBF
Description
Manufacturer
Linear Technology
Datasheet

Specifications of LTM9005IV-AA#PBF

Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTM9005IV-AA#PBF
Manufacturer:
LT
Quantity:
500
FeaTures
applicaTions
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
Typical applicaTion
Fully Integrated “RF-to-Bits” IF-Sampling Receiver
Subsystem
Wide RF Frequency Range: 400MHz to 3.8GHz
140MHz Center Frequency Internal SAW Filter
Low Power ADC with Up to 14-Bit Resolution,
125Msps Sample Rate
16dB Cascaded NF , 17.7dBm Two-Tone IIP3
1.2W Total Power Consumption
50Ω Single-Ended RF and LO Ports
Continuous 20dB Attenuation Range
Internal Bypass Capacitance, No External
Components Required
ADC Clock Duty Cycle Stabilizer
Digital Output Supply Range: 0.5V to 3.6V
15mm × 22mm LGA package
Base Station Receivers
Remote Radio Heads
Communications Test Equipment
LNA
LO
Simplified IF-Sampling Receiver
GAIN
3.3V
SAW
GND
CLK
DescripTion
The LTM
wireless base stations and communications test equip-
ment. Utilizing an integrated System in a Package (SiP)
technology, it includes a downconverting mixer, 140MHz
SAW filter, two gain stages, a variable attenuator and
analog-to-digital converter (ADC). The system is tuned for
an Intermediate Frequency (IF) of 140MHz and a signal
bandwidth of up to 60MHz; contact Linear Technology
regarding customization. The high integration and small
package allow for a very compact receiver.
The high signal level downconverting mixer is optimized
for high linearity, wide dynamic range IF sampling ap-
plications. It includes a high speed differential LO buffer
amplifier driving a double-balanced mixer. Broadband,
integrated transformers on the RF and LO inputs provide
single ended 50Ω interfaces. The RF and LO inputs are
internally matched to 50Ω from 1.6GHz to 2.3GHz.
Versions are available with ADCs up to 14-bit resolution
and 125Msps. A separate output supply allows the parallel
output bus to drive 0.5V to 3.6V logic. A single-ended CLK
input controls converter operation. An optional clock duty
cycle stabilizer allows high performance at full speed for
a wide range of clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
9005 TA01
LTM9005
DAC
Electrical Specifications Subject to Change
®
9005 is an IF Sampling Receiver Subsystem for
OV
0.5V to 3.6V
OGND
DD
IF Sampling Receiver
IF Frequency Response, 64k Point FFT,
–10
–30
–40
–50
–60
–70
–80
–20
0
80
RF = 1.95GHz, LO = 1.81GHz
100
120
IF FREQUENCY (MHz)
Subsystem
140
LTM9005
160
180
200
9005 TA01b
220
1
9005p

Related parts for LTM9005IV-AA#PBF

LTM9005IV-AA#PBF Summary of contents

Page 1

... An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. 3.3V ...

Page 2

... Avoid ultrasonic exposure, the LTM9005 contains a hermetic cavity filter. orDer inForMaTion LEAD FREE FINISH PART MARKING* LTM9005CV-AA#PBF LTM9005V AA LTM9005IV-AA#PBF LTM9005V AA LTM9005CV-AB#PBF LTM9005V AB LTM9005IV-AB#PBF LTM9005V AB Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. ...

Page 3

T SYMBOL PARAMETER RF Input Frequency Range LO Input Frequency Range RF Input Return Loss LO Input Return Loss RF Input Power for –1dBFS LO Input Power Leakage RF ...

Page 4

LTM9005 converTer characTerisTics temperature range, otherwise specifications are at T SYMBOL PARAMETER Resolution (No Missing Codes) Integral Linearity Error (Note 4) Differential Linearity Error gain conTrol The l specifications are 25° 3.3V, RF Input = ...

Page 5

DigiTal inpuTs anD ouTpuTs temperature range, otherwise specifications are at T SYMBOL PARAMETER Logic Inputs (CLK, OE, ADCSHDN) V High Level Input Voltage IH V Low Level Input Voltage IL I Input Current IN C Input Capacitance IN Amplifier Shutdown ...

Page 6

LTM9005 power requireMenTs range, otherwise specifications are at T SYMBOL PARAMETER V Mixer Supply Range CC1 V First Amplifier Supply Range CC2 V Second Amplifier Supply Range CC3 V ADC Analog Supply Voltage DD OV ADC Digital Output Supply Voltage ...

Page 7

TiMing DiagraM t AP ANALOG N INPUT t H CLK – 5 D0-D13 – – 3 Figure 1. Digital Output Bus Timing ...

Page 8

LTM9005 Typical perForMance characTerisTics LTM9005-AA: 64K Point 2-Tone FFT 1949MHz and 1951MHz IN –10 –7dBFS Per Tone SENSE = V –20 DD –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 ...

Page 9

Typical perForMance characTerisTics LTM9005: RF Port Impedance pin FuncTions RF (Pin M3): Single-Ended Input for the RF Signal. This pin is internally connected to the primary side of the RF input transformer, which has low DC resistance to ground. If ...

Page 10

LTM9005 pin FuncTions D0 – D13 (See Table for Pin Locations): Digital Outputs. D13 is the MSB. OF (Pin G15): Over/Under Flow Output. High when an over or under flow has occurred. MODE (Pin F15): Output Format and Clock Duty ...

Page 11

FuncTions Pin Configuration GND V V CC2 CC2 2 GND GND GND 3 GND GND GND 4 GND GND GND 5 GND GND GND 6 GND GND GND 7 GND GND GND ...

Page 12

... The final subsystem is then tested to the exact parameters defined for the application. The final result is a fully integrated, accurately tested and optimized solution in the same package. For more details on the semi-custom receiver subsystem program, contact Linear Technology. 9005p ...

Page 13

Down-Converting Mixer The mixer stage consists of a high linearity double-bal- anced mixer, RF buffer amplifier, high speed limiting LO buffer amplifier and bias/enable circuits. The RF and LO inputs are both single ended. Low side or high side ...

Page 14

LTM9005 applicaTions inForMaTion RF Input Port The RF input is shown in Figure 3 and is internally matched from 1.6GHz to 2.3GHz, requiring no external components over this frequency range. The input return loss, shown in Figure 4, is typically ...

Page 15

RF input impedance and S11 versus frequency (with no external matching) are listed in Table 1 and referenced to Pin M3. The S11 data can be used with a microwave circuit simulator to design custom matching networks and ...

Page 16

LTM9005 applicaTions inForMaTion Custom matching networks can be designed using the port impedance data listed in Table 2. This data is referenced to the LO pin with no external matching. Table 2 LO Input Impedance vs Frequency FREQUENCY INPUT (MHz) ...

Page 17

FERRITE BEAD 0.1µF CLK 100Ω IF LVDS USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR Figure 9. CLK Driver Using an LVDS or PECL to CMOS Converter ETC1-1T CLK 5pF-30pF DIFFERENTIAL CLOCK INPUT 0.1µF FERRITE ...

Page 18

LTM9005 applicaTions inForMaTion Minimum gain is achieved by sinking approximately 10mA from the GAIN pin. If the gain adjusted as part of an active control loop then the circuit in Figure 11 can be used. See the ...

Page 19

Table 4. MODE Pin Function MODE PIN OUTPUT FORMAT 0 Straight Binary 1/3V Straight Binary DD 2/3V 2’s Complement DD V 2’s Complement DD Overflow Bit When OF outputs a logic high the converter is either over- ranged ...

Page 20

LTM9005 applicaTions inForMaTion standard practice recommended that all supply inputs use the same low noise, 3.3V supply, but the ADC and the amplifiers may be operated from a lower voltage level if desired. All three rails can operate ...

Page 21

Recommended Layout The high integration of the LTM9005 makes the PCB board layout very simple and easy. However, to optimize its electri- cal and thermal performance, some layout considerations are still necessary. • Use large PCB copper areas for ground. This helps to dissipate heat in the ...

Page 22

LTM9005 applicaTions inForMaTion DC1391B.zip Layer 1 Layer: top.cmp DC1391B.zip Layer: inner4.lyr Layer Jan 2009,08:23 AM DC1391B.zip Layer 2 Layer: inner1.lyr DC1391B.zip Layer: bottom.sol Layer 4 26 Jan 2009,08:23 AM 9005p ...

Page 23

... SUGGESTED PCB LAYOUT TOP VIEW Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. LGA Package 204-Lead (22mm × ...

Page 24

... Receiver with ADC, Fixed Gain Amplifier and Anti-Alias Filter in 11.25mm × 11.25mm LGA µModule Receiver with Dual ADC, Dual Amplifiers, Anti-Alias Filters and a Dual Trim DAC in 15mm × 11.25mm LGA www.linear.com ● 9005p LT 1010 • PRINTED IN USA  LINEAR TECHNOLOGY CORPORA TION 2010 ...

Related keywords