TS8388BMFS9NB1 E2V, TS8388BMFS9NB1 Datasheet - Page 11

• Manufacturer Part Number: TS8388BMFS9NB1
• Manufacturer: E2V

Specifications of TS8388BMFS9NB1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

3.1
3.2
TSEV8388B - Evaluation Board User Guide
Introduction
Operating
Procedure
This section describes a typical single-ended configuration for analog inputs and clock
inputs.
The single-ended configuration is preferable, as it corresponds to the most straightfor-
ward and quickest TSEV8388B board setting for evaluating the TS8388B at full speed in
the military temperature range.
The inverted analog input V
(on-board 50Ω terminated). In this configuration, no balun transformer is needed to con-
vert properly single-ended mixer output to balanced differential signals for the analog
inputs.
In the same way, no balun is necessary to feed the TS8388B clock inputs with balanced
signals.
Connect directly the RF sources to the in-phase analog and clock inputs of the
converter.
However, dynamic performances can be somewhat improved by entering either analog
or clock inputs in differential mode.
1. Connect the power supplies and Ground accesses
2. The board is set by default for digital outputs in binary format.
3. Connect the CLK clock signal.
(V
banana jacks.
The –5V power supplies should be turned on first.
Note: one single –5V power supply can be used for supplying the digital V
and analog V
The inverted phase clock input CLKB may be left open (as on-board 50Ω termi-
nated). Use a low phase noise RF source. The clock input level is typically
4 dBm and should not exceed +10 dBm into the 50Ω termination resistor (maxi-
mum ratings for clock input power level is 15 dBm). Clock frequency can range
between 10 MHz and 1.4 Gsps.
CC
= +5V, GND = 0V, V
EEA
power planes.
Operating Procedures and
INB
PLUSD
and clock input CLKB common mode level is Ground
= 0V, V
EAE
= V
EED
Characteristics
= –5V) through the dedicated
e2v semiconductors SAS 2009
Section 3
0973D–BDC–02/09
EED
3-1