SSTVF16857DGG NXP Semiconductors, SSTVF16857DGG Datasheet - Page 2

• Manufacturer Part Number: SSTVF16857DGG
• Manufacturer: NXP Semiconductors

Specifications of SSTVF16857DGG

• Logic Family: SSTV
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 14
• Number Of Inputs: 14
• Number Of Outputs: 14
• High Level Output Current: -20mA
• Low Level Output Current: 20mA
• Propagation Delay Time: 1.9ns
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 200(Min)MHz
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
FEATURES
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DESCRIPTION
The SSTVF16857 is a 14-bit SSTL_2 registered driver with
differential clock inputs, designed to operate between 2.3 V and
2.7 V. V
V
be used for standard stub-series applications or capacitive loads.
Master reset (RESET) asynchronously resets all registers to zero.
The SSTVF16857 is intended to be incorporated into standard
DIMM (Dual In-Line Memory Module) designs defined by JEDEC,
such as DDR (Double Data Rate) SDRAM or SDRAM II Memory
Modules. Different from traditional SDRAM, DDR SDRAM transfers
data on both clock edges (rising and falling), thus doubling the peak
bus bandwidth. A DDR DRAM rated at 166 MHz will have a burst
rate of 333 MT/s (mega-transfers per second). The modules require
between 23 and 27 registered control and address lines, so two
14-bit wide devices will be used on each module. The SSTVF16857
is intended to be used for SSTL_2 input and output signals.
The device data inputs consist of differential receivers. One
differential input is tied to the input pin while the other is tied to a
reference input pad, which is shared by all inputs.
The clock input is fully differential to be compatible with DRAM
devices that are installed on the DIMM. However, since the control
inputs to the SDRAM change at only half the data rate, the device
must only change state on the positive transition of the CLK signal.
In order to be able to provide defined outputs from the device even
before a stable clock has been supplied, the device must support an
asynchronous input pin (reset), which when held to the LOW state
will assume that all registers are reset to the LOW state and all
outputs drive a LOW signal as well.
QUICK REFERENCE DATA
GND = 0 V; T
2003 Sep 19
REF
Stub-series terminated logic for 2.5 V V
Optimized for PC 2700 DDR (Double Data Rate) SDRAM
applications
Suitable for PC1600/PC2100 DDR SDRAM applications
Suitable for PC3200 applications when used at V
Inputs compatible with JESD8-9 SSTL_2 specifications.
Flow-through architecture optimizes PCB layout
ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
Latch-up testing is done to JEDEC Standard JESD78, which
exceeds 100 mA.
Full DDR300/333/400 solution @ 2.5V when used with PCKV857
Available in TSSOP-48, TVSOP-48 and 56 ball VFBGA packages
Superior VREF noise rejection
DDR PC1600-PC3200 14-bit SSTL_2 registered
driver with differential clock inputs
normally at 0.5*V
SYMBOL
DDQ
t
PHL
C
/t
must not exceed V
I
amb
PLH
= 25°C; t
DDQ
Propagation delay; CLK to Qn
Input capacitance
r
. The outputs support class I which can
=t
f
v2.5 ns
CC
. Inputs are SSTL_2 type with
PARAMETER
DDQ
(SSTL_2)
DD
= 2.6 V
C
V
L
CC
2
= 30 pF; V
= 2.5 V
PIN CONFIGURATION
CONDITIONS
DDQ
= 2.5 V
V
V
V
V
V
GND
GND
GND
GND
GND
DDQ
Q10
Q12
DDQ
Q13
DDQ
DDQ
DDQ
Q11
Q14
Q5
Q6
Q9
Q1
Q2
Q3
Q4
Q7
Q8
10
12
13
14
15
16
17
18
19
20
21
22
23
24
11
1
2
3
4
5
6
7
8
9
TYPICAL
1.9
2.9
SW00685
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SSTVF16857
D1
D2
GND
V
D3
D4
D5
D6
D7
CLK-
CLK+
V
GND
V
RESET
D8
D9
D10
D11
D12
V
GND
D13
D14
CC
CC
REF
CC
Product data
UNIT
pF
ns