SSTV16857DGG NXP Semiconductors, SSTV16857DGG Datasheet - Page 6

• Manufacturer Part Number: SSTV16857DGG
• Manufacturer: NXP Semiconductors

Specifications of SSTV16857DGG

• Logic Family: SSTV
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 14
• Number Of Inputs: 14
• Number Of Outputs: 14
• High Level Output Current: -20mA
• Low Level Output Current: 20mA
• Propagation Delay Time: 2.4ns
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 200MHz
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
TIMING REQUIREMENTS
Over recommended operating conditions; T
SWITCHING CHARACTERISTICS
Over recommended operating conditions; T
Class I, V
2002 Sep 27
SYMBOL
SYMBOL
t
14-bit SSTL_2 registered driver
with differential clock inputs
PLH
f
f
t
clock
max
PHL
t
t
t
t
su
w
h
/t
PHL
REF
= V
FRONT SIDE
Clock frequency
Pulse duration, CLK, CLK HIGH or LOW
Setup time
Setup time
Hold time
Maximum clock frequency
CLK and CLK
RESET
TT
= V
DDQ
PARAMETER
0.5 and C
(INPUT)
(INPUT)
FROM
184/200-pin DDR SDRAM DIMM
L
= 10 pF (unless otherwise noted) (see Figure 1)
amb
amb
= 0 to +70 C (unless otherwise noted) (see Figure 1)
= 0 to +70 C; V
RESET HIGH before CLK , CLK
The PLL clock distribution device and SSTV registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SSTV16857
Data before CLK , CLK
DDQ
TEST CONDITIONS
= 2.3 – 2.7 V and V
6
SSTV16857
(OUTPUT)
(OUTPUT)
TO
Q
Q
DDQ
PCKV857
does not exceed V
0.75
MIN
MIN
200
1.0
0.2
0.8
1.0
2.0
V
—
V
CC
CC
= 2.5 V 0.2 V
= 2.5 V 0.2 V
LIMITS
LIMITS
CC.
SW00686
MAX
MAX
200
SSTV16857
2.8
4.0
—
—
—
—
—
Product data
UNIT
UNIT
MHz
MHz
ns
ns
ns
ns
ns
ns