AT94K05AL-25AQC Atmel, AT94K05AL-25AQC Datasheet - Page 84

• Manufacturer Part Number: AT94K05AL-25AQC
• Manufacturer: Atmel

Specifications of AT94K05AL-25AQC

• Device System Gates: 5000
• Propagation Delay Time: 12.1ns
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Not Compliant

4.22.3.3
4.22.3.4
84
AT94KAL Series FPSLIC
Scanning 2-wire Serial
Scanning the Clock Pins
The SCL and SDA pins are open drain, bi-directional and enabled separately. The “Enable Out-
put” bits (active High) in the scan chain are supported by general boundary-scan cells. Enabling
the output will drive the pin Low from a tri-state. External pull-ups on the 2-wire bus are required
to pull the pins High if the output is disabled. The “Data Out/In” and “Clock Out/In” bits in the
scan chain are observe-only cells.
chain.
Figure 4-23. Boundary-scan Cells for 2-wire Serial
Figure 4-24
The Enable signal is supported with a general boundary-scan cell, while the oscillator/clock out-
put is attached to an observe-only cell. In addition to the main clock, the timer oscillator is
scanned in the same way. The output from the internal RC-Oscillator is not scanned, as this
oscillator does not have external connections.
Figure 4-24. Boundary-scan Cells for Oscillators and Clock Options
From digital logic
shows how each oscillator with external connection is supported in the scan chain.
previous cell
To 2-wire
Serial Logic
From 2-wire
Serial Logic
From
ShiftDR
0
1
ClockDR UpdateDR
D Q
next
cell
To
Data or Clock Out/In
(Observe Only Cell)
D Q
G
From Previous Cell
To Next Cell
Enable Output
(General Boundary
Scan Cell)
Figure 4-23
EXTEST
0
1
XTAL1/TOSC1
ENABLE
shows how each pin is connected in the scan
Oscillator
XTAL2/TOSC2
OUTPUT
previous cell
From
ShiftDR
0
1
ClockDR
D Q
FF1
SDA or
SCL
next
cell
To
To system logic
1138I–FPSLI–1/08