AT94K05AL-25AQC Atmel, AT94K05AL-25AQC Datasheet - Page 110

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AT94K05AL-25AQC

Manufacturer Part Number
AT94K05AL-25AQC
Description
Manufacturer
Atmel
Datasheet

Specifications of AT94K05AL-25AQC

Device System Gates
5000
Propagation Delay Time
12.1ns
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Mounting
Surface Mount
Pin Count
100
Package Type
PQFP
Lead Free Status / RoHS Status
Not Compliant

Available stocks

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Quantity
Price
Part Number:
AT94K05AL-25AQC
Manufacturer:
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4.27
110
Watchdog Timer
AT94KAL Series FPSLIC
Table 4-22.
Notes:
In up/down PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter advances
from $0000. In overflow PWM mode, the Timer Overflow flag is set as in normal Timer/Counter
mode. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode, i.e., it is
executed when TOV1 is set provided that Timer Overflow Interrupt1 and global interrupts are
enabled. This also applies to the Timer Output Compare1 flags and interrupts.
The Watchdog Timer is clocked from a separate on-chip oscillator which runs at 1 MHz. This is
the typical value at V
By controlling the Watchdog Timer prescaler, the watchdog reset interval can be adjusted, see
Table 4-23 on page 111
the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset
period. If the reset period expires without another watchdog reset, the FPSLIC resets and exe-
cutes from the reset vector.
To prevent unintentional disabling of the watchdog, a special turn-off sequence must be followed
when the watchdog is disabled, see
Figure 4-35. Watchdog Timer
COM1X1
1. In overflow PWM mode, this table is only valid for OCR1X = TOP.
2. X = A or B
1
1
1
1
(2)
PWM Outputs OCR1X = $0000 or TOP
CC
= 3.3V. See characterization data for typical values at other V
for a detailed description. The WDR (watchdog reset) instruction resets
COM1X0
0
0
1
1
(2)
Figure
4-35.
OCR1X
$0000
$0000
TOP
TOP
(1)
(2)
Output OC1X
H
H
L
L
1138I–FPSLI–1/08
(2)
CC
levels.

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