5962-9206203MXA QP SEMICONDUCTOR, 5962-9206203MXA Datasheet - Page 9

• Manufacturer Part Number: 5962-9206203MXA
• Manufacturer: QP SEMICONDUCTOR

Specifications of 5962-9206203MXA

• Lead Free Status / RoHS Status: Supplier Unconfirmed

DSCC FORM 2234
APR 97
1/
2/
3/
4/
5/
6/
7/
8/
9/
10/ This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay
Test
Asynchronous clock input low
Asynchronous clock to local
External asynchronous clock
External feedback maximum
frequency in asynchronous mode
1/(t
Maximum internal asynchronous
Data path maximum frequency in
Maximum asynchronous register
Output data stable time from
time 2/ 7/ 20/
feedback input 4/ 21/
period (1/f
asynchronous mode 4/ 24/
toggle frequency 1/(t
t
asynchronous clock input
4/ 26/
These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
Tested initially and after any design or process changes that affect that parameter, and therefore shall be guaranteed to the
limits specified in table I.
For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 1
second.
May not be tested but shall be guaranteed to the limits specified in table I.
Measured with device programmed as a 16-bit counter in each LAB.
AC tests are performed with input rise and fall times of 6 ns or less, timing reference levels of 1.5 V, input pulse levels of 0
to 3.0 V, and the output loads on figure 3.
This specification is a measure of the delay from input signal applied to a dedicated input to combinatorial output on any
output pin. This delay assumes no expander terms are used to form the logic function. When this note is appled to any
parameter specification it indicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous
preset) is applied to a dedicated input only and no signal path (either clock or data) employs expander logic. If an input
signal is applied to an I/O pin, an additional delay equal to t
input. If expanders are used, add the maximum expander delay t
expanders.
This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay
assumes no expander terms are used to form the logic function.
This specification is a measure of the delay from an input signal applied to a dedicated input to combinatorial output on any
output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander
logic delay for one pass through the expander logic.
assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass
through the expander logic.
frequency 4/ 23/
AWL)
ACO1
DEFENSE SUPPLY CENTER COLUMBUS
4/ 25/
+ t
MICROCIRCUIT DRAWING
AS1
COLUMBUS, OHIO 43218-3990
MAXA4
) 4/ 22/
) 4/
STANDARD
AWH
+
TABLE I. Electrical performance characteristics - Continued.
Symbol
t
t
t
f
f
f
f
t
AWL
ACF
AP
MAXA1
MAXA2
MAXA3
MAXA4
AOH
See figures 3 (circuit A) and
4 6/
unless otherwise specified
-55°C ≤ T
4.5 V ≤ V
Conditions
C
CC
PIA
≤ +125°C
≤ 5.5 V
should be added to the comparable delay for a dedicated
EXP
SIZE
A
to the overall delay for the comparable delay without
Group A
subgroups
9,10,11
REVISION LEVEL
Device
type
B
01
02
03
01
02
03
01
02
03
01
02
03
01
02
03
01
02
03
01
02
03
All
20
11
14
40
25
30
18
27
23
25
40
33.3
22.2
33.3
28.5
25
40
33.3
15
Min
SHEET
Limit
5962-92062
Max
26
18
22
9
MHz
Unit
ns
ns