IPPOSPHYP3 Altera, IPPOSPHYP3 Datasheet - Page 21

• Manufacturer Part Number: IPPOSPHYP3
• Manufacturer: Altera

Specifications of IPPOSPHYP3

• Lead Free Status / RoHS Status: Not Compliant

Chapter 2: Getting Started
POS-PHY Level 2 & 3 Walkthrough
Step 2: Set Up Simulation
© November 2009 Altera Corporation
c
Figure 2–11. Product Order Code
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model
produced by the Quartus II software. It allows for fast functional simulation of IP
using industry-standard VHDL and Verilog HDL simulators.
You may only use these simulation model output files for simulation purposes and
expressly not for synthesis or any other purposes. Using these models for synthesis
will create a nonfunctional design.
To generate an IP functional simulation model for your MegaCore function, follow
these steps:
1. Click Set Up Simulation in IP Toolbench (see
Figure 2–12. IP Toolbench—Set Up Simulation
2. Turn on Generate Simulation Model (see
Preliminary
Figure
Figure 2–12 on page
2–13).
POS-PHY Level 2 and 3 Compiler User Guide
2–9).
2–9