CY7C372I-66YMB Cypress Semiconductor Corp, CY7C372I-66YMB Datasheet - Page 6

• Manufacturer Part Number: CY7C372I-66YMB
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C372I-66YMB

• Family Name: FLASH370i
• # Macrocells: 64
• Number Of Usable Gates: 1600
• Propagation Delay Time: 20ns
• Number Of Logic Blocks/elements: 4
• # I/os (max): 32
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: CLCC
• Memory Type: Flash
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-03033 Rev. *A
Switching Characteristics
Combinatorial Mode Parameters
t
t
t
t
t
Input Registered/Latched Mode Parameters
t
t
t
t
t
t
Output Registered/Latched Mode Parameters
t
t
t
t
t
t
t
f
f
f
t
37x
t
f
Notes:
Parameter
14. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
15. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C372i. This specification is met for
PD
PDL
PDLL
EA
ER
WL
WH
IS
IH
ICO
ICOL
CO
S
H
CO2
SCS
SL
HL
MAX1
MAX2
MAX3
OH
ICS
MAX4
Pipelined Mode Parameters
the devices operating at the same ambient temperature and at the same power supply voltage.
-t
IH
Input to Combinatorial Output
Input to Output Through Transparent Input or
Output Latch
Input to Output Through Transparent Input and
Output Latches
Input to Output Enable
Input to Output Disable
Clock or Latch Enable Input LOW Time
Clock or Latch Enable Input HIGH Time
Input Register or Latch Set-Up Time
Input Register or Latch Hold Time
Input Register Clock or Latch Enable to
Combinatorial Output
Input Register Clock or Latch Enable to Output
Through Transparent Output Latch
Clock or Latch Enable to Output
Set-Up Time from Input to Clock or Latch Enable
Register or Latch Data Hold Time
Output Clock or Latch Enable to Output Delay
(Through Memory Array)
Output Clock or Latch Enable to Output Clock
or Latch Enable (Through Memory Array)
Set-Up Time from Input Through Transparent
Latch to Output Register Clock or Latch Enable
Hold Time for Input Through Transparent Latch
from Output Register Clock or Latch Enable
Maximum Frequency with Internal Feedback in
Output Registered Mode (Least of 1/t
1/(t
Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(t
t
Maximum Frequency with External Feedback
(Lesser of 1/(t
Output Data Stable from Output clock Minus
Input Register Hold Time for 7C37x
Input Register Clock to Output Register Clock
Maximum Frequency in Pipelined Mode (Least
of 1/(t
1/t
WH
SCS
S
), 1/(t
+ t
)
CO
[9]
H
S
+ t
), or 1/t
+ t
IS
H
), 1/t
[1]
), or 1/t
CO
[1]
CO
ICS
Description
+ t
)
CO
S
, 1/(t
[9]
) and 1/(t
[1]
Over the Operating Range
)
[1]
[9]
WL
[1]
+ t
WL
WH
[1]
), 1/(t
+ t
[1]
WH
[1]
[9, 15]
IS
))
SCS
[9]
+ t
[9]
[9]
IH
WL
,
), or
+
153.8
Min.
7C372i-125
83.3
[14]
125
125
5.5
10
3
3
2
2
0
8
0
0
8
Max.
6.5
10
13
15
14
14
14
16
14
153.8
Min.
7C372i-100
100
100
10
12
80
10
3
3
2
2
6
0
0
0
Max.
6.5
12
15
16
16
16
16
18
16
7C372iL-83
Min.
62.5
83.3
125
7C372i-83
12
15
83
12
4
4
3
3
8
0
0
0
Max.
15
18
19
19
19
19
21
19
8
Min.
7C372iL-66
66.6
100
7C372i-66
10
15
20
66
50
15
CY7C372i
4
4
0
5
5
0
0
Page 6 of 13
Max.
20
22
24
24
24
24
26
10
24
MHz
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns