CY7C372I-66YMB Cypress Semiconductor Corp, CY7C372I-66YMB Datasheet - Page 3

• Manufacturer Part Number: CY7C372I-66YMB
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C372I-66YMB

• Family Name: FLASH370i
• # Macrocells: 64
• Number Of Usable Gates: 1600
• Propagation Delay Time: 20ns
• Number Of Logic Blocks/elements: 4
• # I/os (max): 32
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: CLCC
• Memory Type: Flash
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-03033 Rev. *A
Functional Description
Like all members of the F
in I/O resources. Every two macrocells in the device feature
an associated I/O pin, resulting in 32 I/O pins on the
CY7C372i. In addition, there are three dedicated inputs and
two input/clock pins.
Finally, the CY7C372i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect
delays, or expander delays. Regardless of the number of
resources used. or the type of application, the timing param-
eters on the CY7C372i remain the same.
Logic Block
The number of logic blocks distinguishes the members of the
F
Each logic block is constructed of a product term array, a
product term allocator, and 16 macrocells.
Product Term Array
The product term array in the F
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are
available in both positive and negative polarity, making the
overall array size 72 x 86. This large array in each logic block
allows for very complex functions to be implemented in a
single pass through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be imple-
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the F
handled by software and is invisible to the user.
I/O Macrocell
Half of the macrocells on the CY7C372i have separate I/O pins
associated with them. In other words, each I/O pin is shared
by two macrocells. The input to the macrocell is the sum of
between 0 and 16 product terms from the product term
allocator. The macrocell includes a register that can be
optionally bypassed. It also has polarity control, and two global
clocks to trigger the register. The I/O macrocell also features
a separate feedback path to the PIM so that the register can
be buried if the I/O pin is used as an input.
Buried Macrocell
The buried macrocell is very similar to the I/O macrocell.
Again, it includes a register that can be configured as combi-
natorial, as a D flip-flop, a T flip-flop, or a latch. The clock for
this register has the same options as described for the I/O
macrocell. One difference on the buried macrocell is the
addition of input register capability. The user can program the
buried macrocell to act as an input register (D-type or latch)
whose input comes from the I/O pin associated with the neigh-
LASH
LASH
370i family. The CY7C372i includes four logic blocks.
370 PLDs. Note that product term allocation is
LASH
370i family, the CY7C372i is rich
LASH
370i logic block includes
boring macrocell. The output of all buried macrocells is sent
directly to the PIM regardless of its configuration.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
four logic blocks on the CY7C372i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the F
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An
Introduction to In System Reprogramming with F
PCI Compliance
The F
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
F
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term distri-
bution.
3.3V or 5.0V I/O operation
The F
3.3V and 5.0V systems. All devices have two sets of V
one set, V
another set, V
always be connected to a 5.0V power supply. However, the
V
supply, depending on the output requirements. When V
pins are connected to a 5.0V source, the I/O voltage levels are
compatible with 5.0V systems. When V
connected to a 3.3V source, the input voltage levels are
compatible with both 5.0V and 3.3V systems, while the output
voltage levels are compatible with 3.3V systems. There will be
an additional timing delay on all output buffers when operating
in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is
available in commercial and industrial temperature ranges.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In addition to ISR capability, a new feature called bus-hold has
been added to all F
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus
reducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the device without cutting
trace connections to V
Design Tools
Development software for the CY7C372i is available from
Cypress’s Warp™, Warp Professional™, and Warp Enter-
prise™ software packages. Please refer to the data sheets on
these products for more details. Cypress also actively
supports almost all third-party design tools. Please refer to
third-party tool support for further information.
LASH
CCIO
LASH
370i ensures compliance with the PCI AC specifications
LASH
pins may be connected to either a 3.3V or 5.0V power
370i family of CMOS CPLDs are fully compliant with
CCINT
370i family can be configured to operate in both
CCIO
, for internal operation and input buffers, and
, for I/O output drivers. V
LASH
CC
370i I/Os and dedicated input pins.
or GND.
CY7C372i
CCINT
CCIO
Page 3 of 13
LASH
pins must
pins are
LASH
370i.”
CC
pins:
CCIO
370i