CY7C372I-66YMB Cypress Semiconductor Corp, CY7C372I-66YMB Datasheet

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CY7C372I-66YMB

Manufacturer Part Number
CY7C372I-66YMB
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C372I-66YMB

Family Name
FLASH370i
# Macrocells
64
Number Of Usable Gates
1600
Propagation Delay Time
20ns
Number Of Logic Blocks/elements
4
# I/os (max)
32
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-55C to 125C
Operating Temperature Classification
Military
Mounting
Surface Mount
Pin Count
44
Package Type
CLCC
Memory Type
Flash
Lead Free Status / RoHS Status
Not Compliant

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CY7C372I-66YMB
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Cypress Semiconductor Corporation
Document #: 38-03033 Rev. *A
Features
• 64 macrocells in four logic blocks
• 32 I/O pins
• Five dedicated inputs including two clock pins
• In-System Reprogrammable (ISR™) Flash technology
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
• Fully PCI compliant
• 3.3V or 5.0V I/O operation
• Available in 44-pin PLCC, TQFP, and CLCC packages
• Pin-compatible with the CY7C371i
Logic Block Diagram
— JTAG interface
— f
— t
— t
— t
MAX
PD
S
CO
= 5.5 ns
= 10 ns
= 6.5 ns
= 125 MHz
I/O
I/O
8
0
-I/O
-I/O
7
15
8 I/Os
8 I/Os
BLOCK
BLOCK
LOGIC
LOGIC
2
16
MACROCELLS
A
B
3901 North First Street
UltraLogic™ 64-Macrocell Flash CPLD
INPUT
36
16
36
16
INPUTS
PIM
3
Functional Description
The CY7C372i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
all members of the F
designed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic™ F
is electrically erasable and ISR, which simplifies both design
and manufacturing flows, thereby reducing costs. The
Cypress ISR function is implemented through a JTAG serial
interface. Data is shifted in and out through the SDI and SDO
pins. The ISR interface is enabled using the programming
voltage pin (ISR
routability of the F
change existing logic designs while simultaneously fixing
pinout assignments.
The 64 macrocells in the CY7C372i are divided between four
logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
The logic blocks in the F
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
CLOCK
INPUTS
LASH
INPUT/CLOCK
MACROCELLS
2
36
16
36
16
370i™ family of high-density, high-speed CPLDs. Like
BLOCK
BLOCK
LOGIC
LOGIC
San Jose
16
D
C
EN
LASH
2
). Additionally, because of the superior
370i devices, ISR often allows users to
LASH
,
LASH
CA 95134
LASH
370i family, the CY7C372i is
370i architecture are connected
8 I/Os
8 I/Os
370i devices, the CY7C372i
I/O
I/O
Revised April 16, 2004
16
24
-I/O
-I/O
23
CY7C372i
408-943-2600
31

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CY7C372I-66YMB Summary of contents

Page 1

... F change existing logic designs while simultaneously fixing pinout assignments. The 64 macrocells in the CY7C372i are divided between four logic blocks. Each logic block includes 16 macrocells product term array, and an intelligent product term allocator. The logic blocks in the F with an extremely fast and predictable routing resource— ...

Page 2

... The 3.3V I/O mode timing adder must be added to this specification when V 3.3IO Document #: 38-03033 Rev. *A 7C372i-125 7C372i-100 7C372i-83 (ns 5.5 6.0 6.5 6 I/O I/O /SDI CLK / GND I 3.3V. CCIO CY7C372i 7C372iL-83 7C372i- CLCC TopView /SCLK I I ISR GND 12 34 CLK / ...

Page 3

... PIM regardless of its configuration. Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) connects the four logic blocks on the CY7C372i to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM ...

Page 4

... OUT MHz GND Min 0. Min 2. Max Max CY7C372i Ambient V CC Temperature V CCINT 5V ± 0.25V 5V ± 0.25V or 0°C to +70°C −40°C to +85°C 5V ± 0.5V [2] 5V ± 0.5V –55°C to +125°C Min. Typ. [5] 2.4 2.4 [5, 6] [5, 6] [5] 2.0 –0.5 – ...

Page 5

... GND 2.13V(mil) < Output Waveform Measurement Level 0. the V X 0.5V (d) Test Waveforms measured with 35-pF AC Test Load. EA CY7C372i Min. Max 44-Lead CLCC 44-Lead PLCC 2 5 Max. 100 170Ω (com'l) 236Ω (mil) ALL INPUT PULSES 90% 90% 10% 10% < ( Max. ...

Page 6

... All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 15. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C372i. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. ...

Page 7

... Combinatorial Output INPUT COMBINATORIAL OUTPUT Registered Output INPUT CLOCK REGISTERED OUTPUT CLOCK Document #: 38-03033 Rev. *A [14] 7C372i-125 Min. Max. [9] 10 [9] 12 [1] 16 [9] 10 [9] 12 [1] 16 500 CY7C372i 7C372i-83 7C372i-66 7C372i-100 7C372iL-83 7C372iL-66 Min. Max. Min. Max. Min 500 500 500 Max. Unit ns ...

Page 8

... Switching Waveforms (continued) Latched Output INPUT LATCH ENABLE LATCHED OUTPUT Registered Input REGISTERED INPUT INPUT REGISTER CLOCK COMBINATORIAL OUTPUT CLOCK Clock to Clock REGISTERED INPUT INPUT REGISTER CLOCK OUTPUT REGISTER CLOCK Document #: 38-03033 Rev PDL ICS CY7C372i ICO SCS Page ...

Page 9

... Switching Waveforms (continued) Latched Input and Output LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK Asynchronous Preset INPUT REGISTERED OUTPUT CLOCK Document #: 38-03033 Rev ICOL t ICS CY7C372i t PDLL Page ...

Page 10

... Ordering Code 125 CY7C372i-125JC 100 CY7C372i-100JC CY7C372i-100JI 83 CY7C372i-83JC CY7C372i-83JI CY7C372i-83YMB 83 CY7C372iL-83JC 66 CY7C372i-66JC CY7C372i-66JI CY7C372i-66YMB 66 CY7C372iL-66JC Document #: 38-03033 Rev Package Name Package Type J67 44-Lead Plastic Leaded Chip Carrier J67 44-Lead Plastic Leaded Chip Carrier J67 44-Lead Plastic Leaded Chip Carrier J67 ...

Page 11

... MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Switching Characteristics Parameter 10, 11 ICO 10, 11 ICS Package Diagrams Document #: 38-03033 Rev. *A Subgroups Subgroups 44-Lead Plastic Leaded Chip Carrier J67 CY7C372i 51-85003-*A Page ...

Page 12

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 44-Pin Ceramic Leaded Chip Carrier Y67 CY7C372i 51-80014-** Page ...

Page 13

... Document History Page Document Title: CY7C372i UltraLogic™ 64-Macrocell Flash CPLD Document Number: 38-03033 REV. ECN NO. Issue Date ** 106378 06/18/01 *A 213375 See ECN Document #: 38-03033 Rev. *A Orig. of Change Decsription of Change SZV Change from Spec# 38-00498 to 38-03033 FSG Added note to title page: “Use Ultra37000 For All New Designs” ...

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