5962-9759702QXA Cypress Semiconductor Corp, 5962-9759702QXA Datasheet - Page 5

• Manufacturer Part Number: 5962-9759702QXA
• Manufacturer: Cypress Semiconductor Corp

Specifications of 5962-9759702QXA

• Lead Free Status / RoHS Status: Not Compliant

Product Term Sharing
Product term sharing is the process of using the same product
term among multiple macrocells. For example, if more than one
output has one or more product terms in its equation that are
common to other outputs, those product terms are only pro-
grammed once. The F
sharing across groups of four output macrocells in a variable
fashion. The software automatically takes advantage of this ca-
pability—the user does not have to intervene. Note that greater
usable density can often be achieved if the user “floats” the pin
assignment. This allows the compiler to group macrocells that
have common product terms adjacently.
Note that neither product term sharing nor product term steering
have any effect on the speed of the product. All worst-case
steering and sharing configurations have been incorporated in
the timing specifications for the F
F
I/O Macrocell
Within each logic block there are 8 or 16 I/O macrocells depend-
ing on the device used. Figure 4 illustrates the architecture of
the I/O macrocell. The macrocell features a register that can be
configured as combinatorial, a D flip-flop, a T flip-flop, or a lev-
el-triggered latch.
The register can be asynchronously set or asynchronously reset
at the logic block level with the separate set and reset product
terms. Each of these product terms features programmable po-
larity. This allows the registers to be set or reset based on an
AND expression or an OR expression.
Clocking of the register is very flexible. Depending on the de-
vice, either two or four global synchronous clocks are available
to clock the register. Furthermore, each clock features program-
LASH
370i Macrocell
LASH
370i product term allocator allows
LASH
370i devices.
5
mable polarity so that registers can be triggered on falling as
well as rising edges (see the Dedicated/Clock Inputs section).
Clock polarity is chosen at the logic block level.
At the output of the macrocell, a polarity control mux is available
to select active LOW or active HIGH signals. This has the added
advantage of allowing significant logic reduction to occur in
many applications.
The F
separate from the I/O pin input path. This means that if the mac-
rocell is buried (fed back internally only), the associated I/O pin
can still be used as an input.
Buried Macrocell
Some of the devices in the F
macrocells that do not feed individual I/O pins Figure 5. displays
the architecture of the I/O and buried macrocells for these de-
vices. The I/O macrocell is identical to the I/O macrocell for de-
vices without buried macrocells.
The buried macrocell is very similar to the I/O macrocell. Again,
it includes a register that can be configured as combinatorial, a
D flip-flop, a T flip-flop, or a latch. The clock for this register has
the same options as described for the I/O macrocell. The prima-
ry difference between the I/O macrocell and the buried macro-
cell is that the buried macrocell does not have the ability to out-
put data directly to an I/O pin.
One additional difference on the buried macrocell is the addition
of input register capability. The buried macrocell can be config-
ured to act as an input register (D-type or latch) whose input
comes from the I/O pin associated with the neighboring macro-
cell. The output of all buried macrocells is sent directly to the
PIM regardless of its configuration.
LASH
370i macrocell features a feedback path to the PIM
F
LASH
LASH
370i family feature additional
CPLD Family
370i™ ISR™