5962-9759702QXA Cypress Semiconductor Corp, 5962-9759702QXA Datasheet

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5962-9759702QXA

Manufacturer Part Number
5962-9759702QXA
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of 5962-9759702QXA

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
5962-9759702QXA
Quantity:
287
Features
F
Cypress Semiconductor Corporation
• Flash In-System Reprogrammable (ISR™) CMOS
• High density
• Fully PCI compliant
• Bus Hold capabilities on all I/Os and dedicated inputs
• 3.3-V or 5.0-V I/O operation on all devices
• High speed
• Fast Programmable Interconnect Matrix (PIM)
• Intelligent product term allocator
• Simple timing model
LASH
CPLDs
— Combines on board reprogramming with pinout flex-
— Design changes don’t cause pinout or timing chang-
— JTAG interface
— 32–128 macrocells
— 32–128 I/O pins
— Multiple clock pins
— t
— t
— t
— Uniform predictable delay, independent of routing
— 0–16 product terms to any macrocell
— Provides product term steering on an individual ba-
— Provides product term sharing among local macro-
— No fanout delays
Device
371i
372i
373i
374i
375i
ibility and a simple timing model
es
sis
cells
PD
S
CO
370i Selection Guide
= 5–7 ns
= 8.5–10 ns
= 6–7 ns
84/100
84/100
Pins
160
44
44
Macrocells
128
128
32
64
64
3901 North First Street
Dedicated
UltraLogic™ High-Density Flash CPLDs
Inputs
5
5
5
5
5
General Description
The F
high-density programmable logic solutions with unparalleled
performance. Each member of the family is designed with Cy-
press’s state-of-the-art 0.65-micron Flash technology.
All of the UltraLogic F
able and In-System Reprogrammable (ISR), which simplifies
both design and manufacturing flows, thereby reducing costs.
Because of the superior routability of the F
ISR allows users to change existing logic designs without
changing pinout assignments or timing. The Cypress ISR
function is implemented through a JTAG serial interface. Data
is shifted in and out through the SDI and SDO pins, respec-
tively. The ISR interface is enabled from the programming volt-
age pin (ISR
PCI Local Bus specification, meeting all the electrical and tim-
ing requirements. Also, the entire family features bus-hold ca-
pabilities on all I/Os and dedicated inputs. Additionally, the en-
tire family is security bit and user ID supported (when the
security bit is programmed, all locations cannot be verified).
• Flexible clocking
• Security bit and user ID supported
• Packages
I/O Pins
— No expander delays
— No dedicated vs. I/O pin delays
— No additional delay through PIM
— No penalty for using full 16 product terms
— No delay for steering or sharing product terms
— 2–4 clock pins per device
— Clock polarity control
— 44–160 pins
— PLCC, CLCC, PGA, CQFP, and TQFP packages
128
32
32
64
64
LASH
370i™ family of CMOS CPLDs provides a range of
San Jose
EN
). The entire family is fully compliant with the
Flip-Flops
140
140
44
76
76
LASH
F
370i devices are electrically eras-
CA 95134
LASH
Speed (t
8.5
10
10
10
10
CPLD Family
370i™ ISR™
PD
)
LASH
Speed (f
408-943-2600
July 20, 2000
370i devices,
143
125
125
125
125
MAX
)

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5962-9759702QXA Summary of contents

Page 1

... Cypress Semiconductor Corporation UltraLogic™ High-Density Flash CPLDs — No expander delays — No dedicated vs. I/O pin delays — No additional delay through PIM — No penalty for using full 16 product terms — No delay for steering or sharing product terms • ...

Page 2

General Description (continued) The F 370i family is designed to bring the flexibility, ease LASH of use and performance of the 22V10 to high-density CPLDs. The architecture is based on a number of logic blocks that are connected by a ...

Page 3

FROM PRODUCT TERM PIM ARRAY TO PIM Figure 2. Logic Block for CY7C371i, CY7C373i, and CY7C375i (I/O Intensive) 0–16 PRODUCT TERMS MACRO- CELL 6 0–16 PRODUCT TERMS MACRO- CELL 80 PRODUCT 0–16 TERM PRODUCT ALLOCATOR ...

Page 4

FROM PIM PRODUCT TERM ARRAY TO PIM Figure 3. Logic Block for CY7C372i and CY7C374i (Register Intensive) Logic Block The logic block is the basic building block of the F architecture. It consists of a product ...

Page 5

Product Term Sharing Product term sharing is the process of using the same product term among multiple macrocells. For example, if more than one output has one or more product terms in its equation that are common to other outputs, ...

Page 6

FROM PTM 0–16 PRODUCT TERMS FROM PTM 0–16 PRODUCT TERMS ASYNCHRONOUS BLOCK RESET ASYNCHRONOUS 4 SYSTEM CL OCKS (CY7C373i–CY7C375i) BLOCK PRESET 2 SYSTEM CL OCKS (CY7C371i–CY7C372i) f INPUT/CLOCK ...

Page 7

PRODUCT TERMS [ ASYNCHRONOUS BLOCK RESET ASYNCHRONOUS 4 SYSTEM CL OCKS (CY7C373i–CY7C375i) 2 SYSTEM CL OCKS (CY7C371i–CY7C372i) BLOCK PRESET INPUT/CLOCK PIN D 0 FROM CLOCK 1 O POLARITY INPUT 2 ...

Page 8

COMBINATORIALSIGNAL REGISTERED SIGNAL D,T 5 CLOCK Figure 8. Timing Model for CY7C371i not used on the parts. Figure 8 illustrates the true timing model for the 8.5-ns devices. For combinatorial ...

Page 9

... ViewSim and ViewDraw are trademarks of ViewLogic. © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

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