5962-9759702QXA Cypress Semiconductor Corp, 5962-9759702QXA Datasheet - Page 2

• Manufacturer Part Number: 5962-9759702QXA
• Manufacturer: Cypress Semiconductor Corp

Specifications of 5962-9759702QXA

• Lead Free Status / RoHS Status: Not Compliant

General Description
The F
of use and performance of the 22V10 to high-density CPLDs.
The architecture is based on a number of logic blocks that are
connected by a Programmable Interconnect Matrix (PIM).
Each logic block features its own product term array, product
term allocator array, and 16 macrocells. The PIM distributes
signals from the logic block outputs and all input pins to the
logic block inputs.
The family features a wide variety of densities and pin counts
to choose from. At each density there are two packaging op-
tions to choose from—one that is I/O intensive and another
that is register intensive. For example, the CY7C374i and
CY7C375i both feature 128 macrocells. On the CY7C374i,
available in 84-pin packages, half of the macrocells are buried.
On the CY7C375i, available in 160-pin packages, all of the
macrocells are fed to I/O pins. Figure 1 shows a block diagram
of the CY7C374i/5i.
Functional Description
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) consists of a
completely global routing matrix for signals from I/O pins and
feedbacks from the logic blocks. The PIM is an extremely ro-
bust interconnect that avoids fitting and density limitations.
Routing is automatically accomplished by software and the
Logic Block Diagram
LASH
370i family is designed to bring the flexibility, ease
8/16 I/Os
8/16 I/Os
8/16 I/Os
8/16 I/Os
(continued)
BLOCK
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
LOGIC
4
32/64
Figure 1. CY7C374i/5i Block Diagram
A
B
C
D
MACROCELL
INPUT
36
16
36
16
36
16
36
16
INPUTS
1
2
PIM
propagation delay through the PIM is transparent to the user.
Signals from any pin or any logic block can be routed to any or
all logic blocks.
The inputs to the PIM consist of all I/O and dedicated input pins
and all macrocell feedbacks from within the logic blocks. The
number of PIM inputs increases with pin count and the number
of logic blocks. The outputs from the PIM are signals routed to
the appropriate logic block(s). Each logic block receives 36
inputs from the PIM and their complements, allowing for 32-bit
operations to be implemented in a single pass through the
device. The wide number of inputs to the logic block also im-
proves the routing capacity of the F
An important feature of the PIM is simple timing. The propaga-
tion delay through the PIM is accounted for in the timing spec-
ifications for each device. There is no additional delay for trav-
eling through the PIM. In fact, all inputs travel through the PIM.
Likewise, there are no route-dependent timing parameters on
the F
porated in all appropriate F
Routing signals through the PIM is completely invisible to the
user. All routing is accomplished by software—no hand routing
is necessary. Warp™ and third-party development packages
automatically route designs for the F
ter of minutes. Finally, the rich routing resources of the
F
while maintaining fixed pin assignments.
LASH
INPUTS
CLOCK
LASH
370i family accommodate last minute logic changes
4
36
16
36
16
36
16
36
16
INPUT/CLOCK
MACROCELLS
370i devices. The worst-case PIM delays are incor-
BLOCK
LOGIC
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
32/64
H
G
E
F
4
LASH
F
370i specifications.
LASH
LASH
LASH
CPLD Family
370i family.
8/16 I/Os
8/16 I/Os
8/16 I/Os
8/16 I/Os
370i™ ISR™
370i family in a mat-
7C3740i-1