SAA7111AHZV4 NXP Semiconductors, SAA7111AHZV4 Datasheet - Page 13

• Manufacturer Part Number: SAA7111AHZV4
• Manufacturer: NXP Semiconductors

Specifications of SAA7111AHZV4

• Pin Count: 64
• Package Type: LQFP
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
8.11
A missing clock, insufficient digital or analog V
voltages (below 2.7 V) will initiate the reset sequence; all
outputs are forced to 3-state. The indicator output RES is
LOW for approximately 128LLC after the internal reset and
can be applied to reset other circuits of the digital TV
system.
It is possible to force a reset by pulling the chip enable
(CE) to ground. After the rising edge of CE and sufficient
power supply voltage, the outputs LLC, LLC2, CREF,
RTCO, RTS0, RTS1, GPSW and SDA return from 3-state
to active, while HREF, VREF, HS and VS remain in 3-state
and have to be activated via I
(see Table 5).
8.12
The real time control and status output signal contains
serial information about the actual system clock
(increment of the HPLL), subcarrier frequency [increment
and phase (via reset) of the FSC-PLL] and PAL sequence
bit. The signal can be used for various applications in
external circuits, e.g. in a digital encoder to achieve clean
encoding (see Fig.20).
8.13
The text slicer block detects and acquires Line-21 Closed
Captioning data from a 525-line CVBS signal. Extended
data services on Line-21 Field 2 are also supported.
If valid data is detected the two data bytes are stored in two
I
result is stored in the MSB of the corresponding byte.
A third I
ready flags. The two bits F1VAL and F2VAL indicate that
the input signal carries valid Closed Captioning data in the
corresponding fields. The data ready bits F1RDY and
F2RDY have to be evaluated if asynchronous I
reading is used.
1998 May 15
2
C-bus registers. A parity check is also performed and the
Enhanced Video Input Processor (EVIP)
Power-on reset and CE input
RTCO output
The Line-21 text slicer
2
C-bus register is provided for data valid and data
2
C-bus programming
DDA0
2
C-bus
supply
13
8.13.1
There are two methods by which the software can acquire
the data:
1. Synchronous reading once per frame (or once per
2. Asynchronous reading; It can poll either the F1RDY bit
field); It can use either the rising edge (Line-21 Field 1)
or both edges (Line-21 Field 1 or 2) of the ODD signal
(pin RTSO) to initiate an I
three registers 1A, 1B and 1C.
(Line-21 Field 1) or both F1RDY/F2RDY bits (Line-21
Field 1 or 2). After valid data has been read the
corresponding F*RDY bit is set to LOW until new data
has arrived. The polling frequency has to be slightly
higher than the frame or field frequency, respectively.
S
DISPLAY SOFTWARE READING LINE
UGGESTIONS FOR
I
2
C-
2
C-bus read transfer of the
BUS INTERFACE OF THE
Product specification
SAA7111A
-21
DATA