SAA7111AHV4 NXP Semiconductors, SAA7111AHV4 Datasheet - Page 43

• Manufacturer Part Number: SAA7111AHV4
• Manufacturer: NXP Semiconductors

Specifications of SAA7111AHV4

• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
17.2
The I
is reserved for chip version.
17.2.1
Table 11 Chip version SA00; note 1
Note
1. X = reserved.
17.2.2
Table 12 Analog control 1 SA02; note 1
Notes
1. Mode select (see Figs 33 to 40).
2. For modes 0 to 3 use BYPS(SA09,D7) = 0 (chrominance trap active), for modes 4 to 7 use BYPS = 1 (chrominance
Table 13 Analog control 1 SA 02, D5 to D3 (see Fig.14)
1998 May 15
Mode 0 : CVBS (automatic gain)
Mode 1 : CVBS (automatic gain)
Mode 2 : CVBS (automatic gain)
Mode 3 : CVBS (automatic gain)
Mode 4 : Y (automatic gain) + C (gain channel 2 fixed to GAI2 level)
Mode 5 : Y (automatic gain) + C (gain channel 2 fixed to GAI2 level)
Mode 6 : Y (automatic gain) + C (gain channel 2 adapted to Y gain)
Mode 7 : Y (automatic gain) + C (gain channel 2 adapted to Y gain)
Chip version
DECIMAL VALUE
Enhanced Video Input Processor (EVIP)
trap bypassed).
2
C-bus receiver slave address is 48H/49H. Subaddresses 0F, 14, 18, 19, 1D and 1E are reserved; subaddress 01
I
2
C-bus detail
S
S
0....
....7
FUNCTION
UBADDRESS
UBADDRESS
00
02
V1
V2
UPDATE HYSTERESIS FOR 9-BIT GAIN
FUNCTION
ID07
0
0
(2)
ID06
7 LSB
off
0
0
ID05
43
0
1
LOGIC LEVELS
ID04
1
0
MODE 2
ID03
GUDL 2
X
X
0
0
0
0
1
1
1
1
0
1
CONTROL BITS D2 TO D0
CONTROL BITS D5 TO D3
ID02
X
X
MODE 1
GUDL 1
0
0
1
1
0
0
1
1
0
1
Product specification
SAA7111A
ID01
X
X
MODE 0
GUDL 0
0
1
0
1
ID00
0
1
0
1
0
1
X
X