PNX1700EH/G,557 Trident Microsystems, Inc., PNX1700EH/G,557 Datasheet - Page 171

• Manufacturer Part Number: PNX1700EH/G,557
• Manufacturer: Trident Microsystems, Inc.

Specifications of PNX1700EH/G,557

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
2.11.1 Setting GPIO[14:12]/GCLOCK[2:0] as Clock Outputs
2.11.2 GPIO[6:4]/CLOCK[6:4] as Clock Outputs
2.11 GPIO Clocks
direction of the fgpo clock. The output mode (separate or feedback) for the qvcp is
selected by the qvcp_output_select bit. The fgpo_output_select bit selects the mode
(separate or feedback) for the fgpo clock.
Both VDO clocks can also be programmed to have an inverted clock. There are two
possible ways to invert the clock. If the invert clock bit is set then the inverted clock
goes to the IP and the non inverted clock goes to the clock outputs. The qvcp clock is
inverted by setting the invert_qvcp_clock bit in the qvcp configuration register. The
fgpo clock is inverted by setting the invert_fgpo_clock bit in the fgpo configuration
register. Also in output mode the qvcp source clock can be inverted by setting the
sel_clk_qvcp bit to ‘10’. The fgpo source clock can also be inverted by setting the
sel_clk_fgpo bit to ‘10’. By doing this the clock is inverted to both the internal and
external version of the clock. In input mode the clock coming into the chip is inverted
before being sent to the IP. In qvcp this is done by again writing to the
invert_qvcp_clock bit. In fgpo the invert_fgpo_clock bit can also be set to invert the
clock to the IP. In input mode the sel_clk_qvcp does not get used.
For both clocks they come out of reset in a quasi-input/output mode. The pad is set to
be an input and the IP is being driven by the crystal clock (XTAL_IN) and not the input
clock (if any). This is to allow the IP to reset if there isn’t an input clock as well as
protecting an input clock from contention by having the pad set to an input (in the
case of an input clock). In both cases a write to each control register is necessary to
properly put the clock into an input or output configuration (otherwise the logic will
remain in the quasi-input/output mode).
As indicated above VDO_CLK1 can either be QVCP or LCD. After reset the clocks
are in the above mentioned quasi-input/output mode. If it is to be LCD then the
qvcp_out control register must be programmed to “separate” output mode. If the LCD
only bit (bit 31 in the LCD_SETUP MMIO register) is set then the output select bit in
the qvcp_out control register cannot be written to a ‘1’ (feedback mode). The LCD
mode register can only be written to once and then only to disable LCD mode. If this
is done then the output select bit can be programmed to any value.
The folowing sections present the sequence of actions required to enable clocks on
the GPIO[12:14,6:4’ pins.
•
•
•
•
•
•
Set gpio pin to gpio mode 2 using GPIO_MODE_0_15
Set gpio pin to output a 0 using GPIO_MASK_IOD_0_15
Set dds frequency using DDSx_CTL
Enable dds output to clk_gpio_y using CLK_GPIO_y_CTL
page
Enable clk_gpio_y to pin using DDS_OUT_SEL
Set gpio pin to gpio mode 2 using GPIO_MODE_0_15
5-35)
Rev. 1 — 17 March 2006
(Table 11 on page
(Table 16 on page
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
(Table 7 on page
(Table 7 on page
5-35)
(Table 8 on page
(Table 11 on
8-36)
8-24)
8-24)
8-26)
5-20