NQ80331M667 S L9B8 Intel, NQ80331M667 S L9B8 Datasheet - Page 67

• Manufacturer Part Number: NQ80331M667 S L9B8
• Manufacturer: Intel

Specifications of NQ80331M667 S L9B8

• Lead Free Status / RoHS Status: Not Compliant

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Specification Update
V
V
OL1
OH1
Output High Voltage (DDR SDRAM)
Output Low Voltage (DDR SDRAM)
WDTCR also affected by TMR1[3]
The developer’s manual specifies in Section 14.4.2.4 that TMRx, bit[3], (where x = 0 or 1) enables
or disables user-mode writes to the timer registers (TMRx, TCRx, TRRx). However, when
TMR1[3] is set, the Watchdog timer register (WDTCR) is also disabled from user-mode writes.
TMR1[3] also controls the Watchdog timer.
Split Completion Message clarification
Clarification is required for bridge functionality with split completion message.
Add this to section 2.2.13.3.3 between the second and third paragraph:
“If the split completion message indicates the occurrence of a write-data parity error (i.e. - PCI-X
bridge class and write data parity error index), the bridge asserts PERR# and sets the appropriate
bits in the status register when the transaction completes on the conventional interface. The 80331
bridge exhibits this behavior for both the PCI-X bridge class and completer class transactions.
For all other cases in which a non-posted write transaction completes with a split completion
message, the bridge terminates the transaction on the conventional interface with target abort.”
Figure 49 in Design Guide shows incorrect trace length
Figure 49 in the 80331 Design Guide shows incorrect trace length
Figure 49 incorrectly shows the trace length for DQ/DQS/DM as 2.0”-5.0”. The correct trace
length is 2.0”-8.0”, as stated in Tables 58, 59, and 60.
Wrong Voltage Values in Table 21
Table 21 shows wrong voltage values.
Replaced two rows in Table 21. The two rows now appear as follows:
SBR1 Programming When Bank 1 is Unpopulated
Section 8.7.6 incorrectly states: “If bank 1 is unpopulated, SBR1[6:0] is programmed either with
all zeroes or a value equal to SBR0[6:0].”
The sentence should be changed to “If bank 1 is unpopulated, SBR1[6:0] and SBR1[31:30] should
be programmed with a value equal to SBR0[6:0] and SBR0[31:30].”
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®
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80331 I/O Processor Developer’s Manual
80331 I/O Processor Developer’s Manual
80331 I/O Processor Design Guide
80331 I/O Processor Datasheet (273943-003).
80331 I/O Processor Developer’s Manual
1.95
0.35
Intel
Documentation Changes
V
V
®
80331 I/O Processor
I
I
OH
OL
= -12.5 mA (1, 2)
= 12.5 mA (1, 2)
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