NQ80331M667 S L9B8 Intel, NQ80331M667 S L9B8 Datasheet - Page 37

• Manufacturer Part Number: NQ80331M667 S L9B8
• Manufacturer: Intel

Specifications of NQ80331M667 S L9B8

• Lead Free Status / RoHS Status: Not Compliant

52.
Problem:
Implication:
Workaround:
Status:
Specification Update
Note: Disabling the core-to-memory port requires a review of specification clarification 13,
Enabling the core-to-memory port can cause a stall condition
A stall condition can occur during high data throughput to the Memory Controller Unit (MCU),
due to a non-empty Bus Interface Unit (BIU) data queue that might allow no further traffic to be
submitted from the Intel XScale
registers and the associated pointers. The pointers and the queue status bits get out of sync,
allowing part of the BIU to conclude that it is full and therefore not to accept any more
transactions. The other part of the BIU concludes that it is empty, and therefore does not flush the
non-empty condition.
The stall condition can be generated in the following scenario:
Enabling the core-to-memory port (BIUCR.0 = 1, IB address = FFFF_E608h) can cause a stall
condition or data corruption.
Do not enable the core-to-memory port in the BIU Control Register (BIUCR.0). When
BIUCR.0 = 0 (default condition), the core-to-memory port is disabled and forces all Intel XScale
core memory transactions to be issued out the core internal bus (IB) port, therefore avoiding the
stall condition.
Interface Unit follows PCI ordering rules” on page
Fixed. Fixed in D-0 stepping. See the
1. Within the MCU, accept a read from one port (core-to-memory or IB-MCU). This triggers an
2. An “incoherent” write (in other words, a write that must precede the read from step 1) must
3. A read must also exist in the opposite port; destination (coherent or incoherent) is unimportant.
4. An incoherent write arrives in the original port during the exact cycle the opposite write is
5. Due to the combination of pending read request and last-second incoherent write, the MCU
automatic coherency check, which requires writes within the same 1 K address “page” to be
pushed ahead of the read.
exist in the opposite port. This write is executed to DDR memory as normal.
This has the effect of maintaining the port’s request to the MCU.
completed.
gets out of sync and attempts to acknowledge a write from the wrong port. This causes the
offending queue pointer/status bit mismatch. This situation locks the opposite port to the
original read transaction.
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core. The stall is due to an invalid state in the queue control
Table , “Summary Table of Changes” on page
54.
Intel
®
80331 I/O Processor
Non-Core Errata
9.
“Bus
37
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