NQ80331M667 S L9B8 Intel, NQ80331M667 S L9B8 Datasheet - Page 22

• Manufacturer Part Number: NQ80331M667 S L9B8
• Manufacturer: Intel

Specifications of NQ80331M667 S L9B8

• Lead Free Status / RoHS Status: Not Compliant

Intel
Non-Core Errata
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®
80331 I/O Processor
SDCR0.2 implemented as ‘Reserved’
The attribute for bit 2 in the MCU SDRAM Control Register 0 (SDCR0) is incorrectly
implemented as ‘Reserved’, instead of ‘Read Only’. Since it is ‘reserved’, software cannot rely on
reading this bit to determine when DDR or DDR-II memory type is selected. The external state of
MEM_TYPE can not be correctly identified by reading this bit.
This bit cannot be used to determine memory type.
Since hardware design is specific to either DDR or DDR-II, software engineers know what
memory is being used in their application and therefore need not rely on this bit. Also, software can
read DIMM information via Serial Presence Detect (SPD).
Fixed. Fixed in B-0 stepping. See the
32-bit region missing proper address decode
When connected to 64-bit SDRAM, a 32-bit region can be defined by the S32SR register. There is an
issue with the calculation that is performed to determine whether a transaction is in the 32-bit window
or not. The MCU address decoder is missing the MSB for the 32-bit region hit/miss. This issue only
applies to systems that intend to use the 32-bit region. There are no other base address restrictions.
32-bit addresses can be decoded improperly causing unstable code execution.
Do not allow the base address, defined by SDBR, to be aligned on an odd 1G boundary (e.g., bit 30
cannot be set to a ‘1’:
Fixed. Fixed in B-0. See the
S_GNT[3:2]# outputs are not pulled high when Bridge is disabled.
When the bridge is disabled (BRG_EN = 0), the S_GNT[3:2]# signals float (Z). These signals need
to not float, but be pulled high (H).
No negative impact expected.
External pull-ups are required.
Fixed. Fixed in B-0 stepping. See the
Split Transaction Commitment limit register mechanism, in the PCI-X
bridge, does not operate as implied by the PCI-X Addendum to the PCI
Local Bus Specification, Revision 1.0a
The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a requires that the bridge
operate in a fully buffered mode. The 80331 bridge allows software to write the Split Transaction
limit register, to allow compatibility with existing software, however, it behaves as though the
register is programmed with a value FFFFh. The bridge forwards all split transactions without
regard to the sequence size or the amount of available buffer space.
This behavior could result in the bridge split completion buffers becoming full, while additional
split completions are being received. When this situation occurs, the bridge either issues a retry or
disconnects on the next ADB, until buffer space is available.
No workaround.
No Fix. Not to be fixed. See the
For example, allowable base addresses: 0x8000_0000, 0xA000_0000, 0x2000_0000
Non-allowable base addresses: 0x4000_0000, 0xC000_0000, 0x4100_0000
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
9.
Specification Update
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