MC9S12DG128VPVE Freescale, MC9S12DG128VPVE Datasheet - Page 61

• Manufacturer Part Number: MC9S12DG128VPVE
• Manufacturer: Freescale

Specifications of MC9S12DG128VPVE

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 50MHz
• Interface Type: SCI/SPI/I2C/CAN
• Total Internal Ram Size: 8KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.25V
• Operating Supply Voltage (min): 2.25/2.35/4.5V
• On-chip Adc: 2(8-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Lead Free Status / RoHS Status: Compliant

Function 1
Freescale Semiconductor
Pin Name
PAD[14:8]
VREGEN
PAD[6:0]
PAD[15]
RESET
PB[7:0]
PA[7:0]
EXTAL
PAD[7]
BKGD
TEST
XTAL
XFC
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PH7
Function 2
ADDR[15:8]/
Pin Name
ADDR[7:0]/
DATA[15:8]
DATA[7:0]
AN1[6:0]
AN0[6:0]
NOACC
AN1[7]
LSTRB
AN0[7]
IPIPE1
IPIPE0
TAGHI
KWH7
ECLK
XIRQ
R/W
IRQ
—
—
—
—
—
—
Function 3
Pin Name
ETRIG1
ETRIG0
XCLKS
TAGLO
MODC
MODB
MODA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
---
Function 4
Table 2-1 Signal Properties
Pin Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Function 5
Pin Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Device User Guide — 9S12DT128DGV2/D V02.16
Powered
VDDPLL
VDDPLL
VDDPLL
VDDR
VDDX
VDDR
VDDA
VDDA
VDDA
VDDA
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
N.A.
by
PUPBE
PUPEE
PUPEE
PUPAE
Always
PUCR/
PUCR/
PUCR/
PUCR/
PERH/
While RESET pin
PPSH
CTRL
None
None
None
None
None
None
NA
NA
NA
NA
Up
Internal Pull
Resistor
Down
low:
Disabled Port H I/O, Interrupt
Disabled
Disabled
depen-
depen-
Reset
State
None
None
Mode
Mode
None
None
None
None
dant
dant
NA
NA
NA
NA
Up
Up
1
1
Oscillator Pins
External Reset
Test Input
Voltage Regulator
Enable Input
PLL Loop Filter
Background Debug,
Tag High, Mode Input
Port AD Input,
Analog Inputs,
External Trigger
Input (ATD1)
Port AD Input,
Analog Inputs
(ATD1)
Port AD Input, Analog
Inputs, External
Trigger Input (ATD0)
Port AD Input, Analog
Inputs (ATD0)
Port A I/O,
Multiplexed
Address/Data
Port B I/O,
Multiplexed
Address/Data
Port E I/O, Access,
Clock Select
Port E I/O, Pipe
Status, Mode Input
Port E I/O, Pipe
Status, Mode Input
Port E I/O, Bus Clock
Output
Port E I/O, Byte
Strobe, Tag Low
Port E I/O, R/W in
expanded modes
Port E Input,
Maskable Interrupt
Port E Input, Non
Maskable Interrupt
Description
61