XC56309AG100A Freescale, XC56309AG100A Datasheet - Page 6

• Manufacturer Part Number: XC56309AG100A
• Manufacturer: Freescale

Specifications of XC56309AG100A

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Compliant

Signals/Connections
1-2
Notes:
During
Reset
PINIT
AA[0–3]/RAS[0–3]
1.
2.
3.
4.
CLKOUT
A[0–17]
D[0–23]
GND
EXTAL
V
V
GND
GND
GND
GND
GND
GND
GND
PCAP
Reset
V
V
V
XTAL
BCLK
BCLK
V
CCQH
V
V
After
CCQL
The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or
double Host Request (HR) configurations. Since each of these modes is configured independently, any combination
of these modes is possible. These HI08 signals can also be configured alternatively as GPIO signals (PB[0–15]).
Signals with dual designations (for example, HAS/HAS) have configurable polarity.
The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals
(PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.
TIO[0–2] can be configured as GPIO signals.
Ground connections shown in this figure are for the TQFP package. In the MAP-BGA package, in addition to the
GND
CAS
NMI
CCP
CCA
CCD
CCC
CCH
CCS
WR
RD
BR
BG
BB
TA
P1
Q
D
C
H
P
A
S
P
and GND
4
4
2
2
4
3
3
4
2
2
18
24
4
P1
Power Inputs:
PLL
Internal Logic
I/O
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer
Grounds
PLL
PLL
Internal Logic
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer
Port A
Clock
External
Address Bus
External
Data Bus
External
Bus
Control
PLL
Figure 1-1.
connections, there are 64 GND connections to a common internal package ground plane.
4
:
DSP56309
DSP56309 Technical Data, Rev. 7
Signals Identified by Functional Group
Interface (SCI) Port
Synchronous Serial
Synchronous Serial
Communications
Interface Port 0
Interface Port 1
Mode Control
(HI08) Port
JTAG Port
Enhanced
Enhanced
Interrupt/
Interface
(ESSI0)
(ESSI1)
Timers
OnCE/
Serial
Host
1
2
2
2
3
3
3
8
TIO0
TIO1
TIO2
During Reset
MODA
MODB
MODC
MODD
RESET
Non-Multiplexed
Bus
H[0–7]
HA0
HA1
HA2
HCS/HCS
Single DS
HRW
HDS/HDS
Single HR
HREQ/HREQ
HACK/HACK
SC0[0–2]
SCK0
SRD0
STD0
SC1[0–2]
SCK1
SRD1
STD1
RXD
TXD
SCLK
TCK
TDI
TDO
TMS
TRST
DE
After Reset
Port C GPIO
PC[0–2]
PC3
PC4
PC5
Port D GPIO
PD[0–2]
PD3
PD4
PD5
Port E GPIO
PE0
PE1
PE2
Timer GPIO
TIO0
TIO1
TIO2
IRQA
IRQB
IRQC
IRQD
RESET
Multiplexed
Bus
HAD[0–7]
HAS/HAS
HA8
HA9
HA10
Double DS
HRD/HRD
HWR/HWR
Double HR
HTRQ/HTRQ
HRRQ/HRRQ
Freescale Semiconductor
Port B
GPIO
PB[0–7]
PB8
PB9
PB10
PB13
PB11
PB12
PB14
PB15