CY8C5246AXI-038 Cypress Semiconductor Corp, CY8C5246AXI-038 Datasheet - Page 18

• Manufacturer Part Number: CY8C5246AXI-038
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5246AXI-038

• Lead Free Status / RoHS Status: Compliant

Table 6-1. Oscillator Summary
6.1.1 Internal Oscillators
6.1.1.1 Internal Main Oscillator
In most designs the IMO is the only clock source required, due
to its ±1% accuracy. The IMO operates with no external
components and outputs a stable clock. A factory trim for each
frequency range is stored in the device. With the factory trim,
tolerance varies from ±1% at 3 MHz, up to ±4% at 24 MHz. The
IMO, in conjunction with the PLL, allows generation of CPU and
system clocks up to the device's maximum frequency (see
Clock
24 MHz.
Document Number: 001-55034 Rev. *G
MHzECO
kHzECO
Source
Doubler
IMO
DSI
PLL
Domain). The IMO provides clock outputs at 3, 6, 12, and
ILO
7
24 MHz
12 MHz
32 kHz
3 MHz
4 MHz
0 MHz
12-48 MHz
1 kHz
Fmin
3-24 MHz
Doubler
IMO
Divider 16 bit
Divider 16 bit
Divider 16 bit
Divider 16 bit
Digital Clock
Digital Clock
Digital Clock
Digital Clock
±1% over voltage and temperature
Crystal dependent
Input dependent
Input dependent
Input dependent
–50%, +100%
Crystal dependent
4-33 MHz
ECO
Tolerance at Fmin
24-40 MHz
PLL
PRELIMINARY
Figure 6-1. Clocking Subsystem
External IO
0-40 MHz
or DSI
Clock Mux
Divider 16 bit
Divider 16 bit
Divider 16 bit
Divider 16 bit
Digital Clock
Digital Clock
Digital Clock
Digital Clock
USB
System
32 kHz ECO
6.1.1.2 Clock Doubler
The clock doubler outputs a clock at twice the frequency of the
input clock. The doubler works for input frequency ranges of 6 to
24 MHz (providing 12 to 48 MHz at the output). It can be
configured to use a clock from the IMO, MHzECO, or the DSI
(external pin). The doubler is typically used to clock the USB.
6.1.1.3 Phase-Locked Loop
The PLL allows low frequency, high accuracy clocks to be
multiplied to higher frequencies. This is a tradeoff between
higher clock frequency and accuracy and, higher power
consumption and increased startup time. The PLL block provides
PSoC
100 kHz
24 MHz
33 MHz
40 MHz
40 MHz
48 MHz
32 kHz
Fmax
1,33,100 kHz
®
ILO
±4%
Crystal dependent
Input dependent
Input dependent
Input dependent
–55%, +100%
Crystal dependent
5: CY8C52 Family Datasheet
Tolerance at Fmax
7
Bus Clock Divider
Analog Clock
Divider 16 bit
Analog Clock
Divider 16 bit
Analog Clock
Divider 16 bit
Analog Clock
Divider 16 bit
16 bit
w
w
w
w
s
k
e
s
k
e
s
k
e
s
k
e
10 µs max
5 ms typ, max is
crystal dependent
Input dependent
250 µs max
1 µs max
15 ms max in lowest
power mode
500 ms typ, max is
crystal dependent
Clock
Startup Time
CPU
Clock
Bus
Page 18 of 85
[+] Feedback