CY8C5246AXI-038 Cypress Semiconductor Corp, CY8C5246AXI-038 Datasheet - Page 17

• Manufacturer Part Number: CY8C5246AXI-038
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5246AXI-038

• Lead Free Status / RoHS Status: Compliant

Table 5-3. Peripheral Data Address Map
The bit-band feature allows individual bits in words in the
bit-band region to be read or written as atomic operations. This
is done by reading or writing bit 0 of corresponding words in the
bit-band alias region. For example, to set bit 3 in the word at
address 0x20000000, write a 1 to address 0x2200000C. To test
the value of that bit, read address 0x2200000C and the result is
either 0 or 1 depending on the value of the bit.
Most memory accesses done by the Cortex-M3 are aligned, that
is, done on word (4-byte) boundary addresses. Unaligned
accesses of words and 16-bit half-words on nonword boundary
addresses can also be done, although they are less efficient.
5.6.2 Address Map and Cortex-M3 Buses
The ICode and DCode buses are used only for accesses within
the Code address range, 0 - 0x1FFFFFFF.
Document Number: 001-55034 Rev. *G
0x00000000 – 0x0003FFFF 256 K Flash
0x1FFF8000 – 0x1FFFFFFF 32 K SRAM in Code region
0x20000000 – 0x20007FFF 32 K SRAM in SRAM region
0x40004000 – 0x400042FF Clocking, PLLs, and oscillators
0x40004300 – 0x400043FF Power management
0x40004500 – 0x400045FF Ports interrupt control
0x40004700 – 0x400047FF Flash programming interface
0x40004800 – 0x400048FF Cache controller
0x40004900 – 0x400049FF I
0x40004E00 – 0x40004EFF Decimator
0x40004F00 – 0x40004FFF Fixed timer/counter/PWMs
0x40005000 – 0x400051FF I/O ports control
0x40005400 – 0x400054FF External Memory Interface
0x40005800 – 0x40005FFF Analog Subsystem Interface
0x40006000 – 0x400060FF USB Controller
0x40006400 – 0x40006FFF UDB Configuration
0x40007000 – 0x40007FFF PHUB Configuration
0x40008000 – 0x400087FF EEPROM
0x4000A000 – 0x4000A400 CAN
0x40010000 – 0x4001FFFF Digital Interconnect Configuration
0x48000000 – 0x48007FFF Flash ECC Bytes
0x60000000 – 0x60FFFFFF External Memory Interface
0xE0000000 – 0xE00FFFFF Cortex-M3 PPB Registers,
Address Range
(EMIF) control registers
(EMIF)
including NVIC, debug, and trace
2
C controller
Purpose
PRELIMINARY
The system bus is used for data accesses and debug accesses
within the ranges 0x20000000 - 0xDFFFFFFF and 0xE0100000
- 0xFFFFFFFF. Instruction fetches can also be done within the
range 0x20000000 - 0x3FFFFFFF, although these can be slower
than instruction fetches via the ICode bus.
The private peripheral bus (PPB) is used within the Cortex-M3 to
access system control registers and debug and trace module
registers.
6. System Integration
6.1 Clocking System
The clocking system generates, divides, and distributes clocks
throughout the PSoC system. For the majority of systems, no
external crystal is required. The IMO and PLL together can
generate up to a 40 MHz clock, accurate to ±1% over voltage and
temperature. Additional internal and external clock sources allow
each design to optimize accuracy, power, and cost. All of the
system clock sources can be used to generate other clock
frequencies in the 16-bit clock dividers and UDBs for anything
you want, for example a UART baud rate generator.
Clock generation and distribution is automatically configured
through the PSoC Creator IDE graphical interface. This is based
on the complete system’s requirements. It greatly speeds the
design process. PSoC Creator allows designers to build clocking
systems with minimal input. The designer can specify desired
clock frequencies and accuracies, and the software locates or
builds a clock that meets the required specifications. This is
possible because of the programmability inherent PSoC.
Key features of the clocking system include:
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Seven general purpose clock sources
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IMO has a USB mode that auto-locks to the USB bus clock
requiring no external crystal for USB. (USB equipped parts
only)
Independently sourced clock dividers in all clocks
Eight 16-bit clock dividers for the digital system
Four 16-bit clock dividers for the analog system
Dedicated 16-bit divider for the CPU bus and CPU clock
Automatic clock configuration in PSoC Creator
PSoC
3- to 24-MHz IMO, ±1% at 3 MHz
4- to 33-MHz external crystal oscillator (MHzECO)
Clock doubler provides a doubled clock frequency output for
the USB block, see
DSI signal from an external I/O pin or other logic
24- to 40-MHz fractional phase-locked loop (PLL) sourced
from IMO, MHzECO, or DSI
Clock Doubler
1-kHz, 33-kHz, 100-kHz ILO for watchdog timer (WDT) and
Sleep Timer
32.768-kHz external crystal oscillator (ECO) for RTC
®
5: CY8C52 Family Datasheet
USB Clock Domain
on page 20.
Page 17 of 85
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