CY8C5487LTI-007 Cypress Semiconductor Corp, CY8C5487LTI-007 Datasheet - Page 56

• Manufacturer Part Number: CY8C5487LTI-007
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5487LTI-007

• Lead Free Status / RoHS Status: Compliant

the data clock and the other is used for data input and output.
SWD can be enabled on only one of the pin pairs at a time. This
only happens if, within 8 µs (key window) after reset, that pin pair
(JTAG or USB) receives a predetermined sequence of 1s and 0s.
SWD is used for debugging or for programming the flash
memory.
The SWD interface can be enabled from the JTAG interface or
disabled, allowing its pins to be used as GPIO. Unlike JTAG, the
SWD interface can always be reacquired on any device during
the key window. It can then be used to reenable the JTAG
interface, if desired. When using SWD or JTAG pins as standard
GPIO, make sure that the GPIO functionality and PCB circuits do
not interfere with SWD or JTAG use.
9.3 Debug Features
The CY8C54 supports the following debug features:
9.4 Trace Features
The following trace features are supported:
Document Number: 001-55036 Rev. *F
Halt and single-step the CPU
View and change CPU and peripheral registers, and RAM
addresses
Six program address breakpoints and two literal access break-
points
Data watchpoint events to CPU
Patch and remap instruction from flash to SRAM
Debugging at the full speed of the CPU
Debug operations are possible while the device is reset, or in
low power modes
Compatible with PSoC Creator and MiniProg3 programmer and
debugger
Standard JTAG programming and debugging interfaces make
CY8C54 compatible with other popular third-party tools (for
example, ARM / Keil)
Instruction trace
Data watchpoint on access to data address, address range, or
data value
Trace trigger on data watchpoint
Debug exception trigger
Code profiling
Counters for measuring clock cycles, folded instructions,
load/store operations, sleep cycles, cycles per instruction,
interrupt overhead
Interrupt events trace
Software event monitoring, “printf-style” debugging
PRELIMINARY
9.5 SWV and TRACEPORT Interfaces
The SWV and TRACEPORT interfaces provide trace data to a
debug host via the Cypress MiniProg3 or an external trace port
analyzer. The 5 pin TRACEPORT is used for rapid transmission
of large trace streams. The single pin SWV mode is used to
minimize the number of trace pins. SWV is shared with a JTAG
pin. If debugging and tracing are done at the same time then
SWD may be used with either SWV or TRACEPORT, or JTAG
may be used with TRACEPORT, as shown in
Table 9-1. Debug Configurations
9.6 Programming Features
The JTAG and SWD interfaces provide full programming
support. The entire device can be erased, programmed, and
verified. Designers can increase flash protection levels to protect
firmware IP. Flash protection can only be reset after a full device
erase. Individual flash blocks can be erased, programmed, and
verified, if block security settings permit.
9.7 Device Security
PSoC 5 offers an advanced security feature called device
security, which permanently disables all test, programming, and
debug ports, protecting your application from external access.
The device security is activated by programming a 32-bit key
(0x50536F43) to a Write Once Latch (WOL).
The Write Once Latch is a type of nonvolatile latch (NVL). The
cell itself is an NVL with additional logic wrapped around it. Each
WOL device contains four bytes (32 bits) of data. The wrapper
outputs a ‘1’ if a super-majority (28 of 32) of its bits match a
pre-determined pattern (0x50536F43); it outputs a ‘0’ if this
majority is not reached. When the output is 1, the Write Once NV
latch locks the part out of Debug and Test modes; it also perma-
nently gates off the ability to erase or alter the contents of the
latch. Matching all bits is intentionally not required, so that single
(or few) bit failures do not deassert the WOL output. The state of
the NVL bits after wafer processing is truly random with no
tendency toward 1 or 0.
The WOL only locks the part after the correct 32-bit key
(0x50536F43) is loaded into the NVL's volatile memory,
programmed into the NVL's nonvolatile cells, and the part is
reset. The output of the WOL is only sampled on reset and used
to disable the access. This precaution prevents anyone from
reading, erasing, or altering the contents of the internal memory.
All debug and trace disabled
JTAG
SWD
SWV
TRACEPORT
JTAG + TRACEPORT
SWD + SWV
SWD + TRACEPORT
Debug and Trace Configuration
PSoC
®
5: CY8C54 Family Data
GPIO Pins Used
Table
9 or 10
4 or 5
0
2
1
5
3
7
9-1.
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