LH79524N0F100A1 NXP Semiconductors, LH79524N0F100A1 Datasheet - Page 51

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LH79524N0F100A1

Manufacturer Part Number
LH79524N0F100A1
Description
Microcontrollers (MCU) LCD USB ETH'NET MMU LFBGA208
Manufacturer
NXP Semiconductors
Datasheet

Specifications of LH79524N0F100A1

Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Applications
Embedded Control
Processing Unit
Microcontroller
Operating Supply Voltage (min)
1.7/3V
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.9/3.6V
Package Type
LFBGA
Screening Level
Industrial
Pin Count
208
Mounting
Surface Mount
Rad Hardened
No
Data Bus Width
32 bit
Program Memory Type
ROMLess
Data Ram Size
16 KB
Interface Type
I2C, I2S, IrDA, SSP, UART, USB
Maximum Clock Frequency
76.205 MHz
Number Of Programmable I/os
108
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
LFBGA
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LH79524N0F100A1
Manufacturer:
HONEYWELL
Quantity:
3 000
Part Number:
LH79524N0F100A1,55
Manufacturer:
NXP Semiconductors
Quantity:
10 000
System-on-Chip
Product data sheet
NOTE: LCDDCLK can range from 4.5 MHz to 6.8 MHz.
NOTE:
SYNCHRONIZATION)
*
SYNCHRONIZATION
(LCD VIDEO DATA)
*
(INTERNAL)
APBPERIPHCLKCTRL1:LCD
CLKPRESCALE:LCDPS
(SHOWN FOR REFERENCE)
Source is RCPC.
CLCDCLK
(HORIZONTAL
LCDEN
(INTERNAL DATA ENABLE)
(VERTICAL
LCDVD[11:0]
LCDSPS
LCDVD[11:0] (LH79525)
LCDVD[15:0] (LH79524)
16 × (TIMING0:PPL+1)
PULSE)
LCDVD[11:0] (LH79525)
LCDVD[15:0] (LH79524)
(DELAYED FOR
AD-TFT, HR-TFT)
LCDLP
LCDSPL
(AD-TFT, HR-TFT
START PULSE LEFT)
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
LCDDCLK
(DELAYED FOR
AD-TFT, HR-TFT)
LCDDCLK
(PANEL CLOCK)
TIMING2:PCD
TIMING2:BCD
TIMING2:IPC
TIMING2:CPL
LCDREV
LCDCLS
LCDPS
1.5 µs - 4 µs
Figure 32. AD-TFT, HR-TFT Horizontal Timing
AD-TFT and HR-TFT SIGNALS ARE TFT SIGNALS, RE-TIMED
TIMING1:VSW
Figure 33. AD-TFT, HR-TFT Vertical Timing
TIMING0:HSW
ALITIMING1:PSCLS
ALITIMING1:LPDEL
TIMING0:HSW +
ALITIMING2:SPLDEL
TIMING0: HBP
Rev. 02 — 17 March 2009
NXP Semiconductors
1 LCDDCLK
1 LCDDCLK
001
002 003 004 005 006 007 008
1 AD-TFT or HR-TFT HORIZONTAL LINE
001
ALITIMING2:PS2CLS2
002 003 004 005 006
PIXEL DATA
320
317
318
319 320
LH79524/LH79525
LH79525-42
LH79525-43
51

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