ISP1160BM,518 NXP Semiconductors, ISP1160BM,518 Datasheet - Page 28

• Manufacturer Part Number: ISP1160BM,518
• Manufacturer: NXP Semiconductors

Specifications of ISP1160BM,518

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table 6.
ISP1160-01_7
Product data sheet
Observed items
HcBufferStatus register
Bit 2 (ATLBufferFull)
Bit 5 (ATLBufferDone)
USB traffic on USB Bus
Run results of the C program example
9.5 HC operational model
Upon power up, the HCD sets up all operational registers (32-bit). The
FSLargestDataPacket field (bits 30 to 16) of the HcFmInterval register (0DH to read, 8DH
to write) and the HcLSThreshold register (11H to read, 91H to write) determine the end of
the frame for full-speed and low-speed packets. By programming these fields, the
effective USB bus usage can be changed. Furthermore, the size of the ITL buffers
(HcITLBufferLength, 2AH to read, AAH to write) is programmed.
If a USB frame contains both ISO and AT packets, two interrupts will be generated per
frame.
One interrupt is issued concurrently with the SOF. This interrupt (ITLInt is set in the
HcμPInterrupt register) triggers reading and writing of the ITL buffer by the
microprocessor, after which the interrupt is cleared by the microprocessor.
Next the programmable ATL Interrupt (bit ATLInt is set in the HcμPInterrupt register) is
issued, which triggers reading and writing of the ATL buffer by the microprocessor, after
which the interrupt is cleared by the microprocessor. If the microprocessor cannot handle
the ISO interrupt before the next ISO interrupt, disrupted ISO traffic can result.
To be able to send more than one packet to the same Control or Bulk endpoint in the
same frame, the Active bit and the TotalBytes field are introduced (see
is cleared only if all data of the Proprietary Transfer Descriptor (PTD) have been
transferred or if a transaction at that endpoint contained a fatal error. If all PTDs of the ATL
are serviced once and the frame is not over yet, the HC starts looking for a PTD with
bit Active still set. If such a PTD is found and there is still enough time in this frame,
another transaction is started on the USB bus for this endpoint.
For ISO processing, the HCD also has to take care of the BufferStatus register (2CH, read
only) for the ITL buffer RAM operations. After the HCD writes ISO data into ITL buffer
RAM, the ITL0BufferFull or ITL1BufferFull bit (depending on whether it is ITL0 or ITL1) will
be set to logic 1.
After the HC processes the ISO data in the ITL buffer RAM, the corresponding
ITL0BufferDone or ITL1BufferDone bit will automatically be set to logic 1.
The HCD can clear the buffer status bits by a read of the ITL buffer RAM. This must be
done within the 1 ms frame from which ITL0BufferDone or ITL1BufferDone was set.
Failure to do so will cause the ISO processing to stop and a power-on reset or software
reset will have to be applied to the HC, a USB reset to the USB bus must not be made.
HC not initialized and not in
USBOperational state
no
1
0
Rev. 07 — 29 September 2009
…continued
HC initialized and in
USBOperational state
yes
1
1
Embedded USB host controller
Comments
transfer completed
PTD data processed by HC
OUT packets can be seen
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
Table
5). Bit Active
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