CS9211-VNG National Semiconductor, CS9211-VNG Datasheet - Page 35

• Manufacturer Part Number: CS9211-VNG
• Manufacturer: National Semiconductor

Specifications of CS9211-VNG

• Operating Temperature (max): 85C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Revision 2.1
Functional Description
3.2.9
The problem with displaying pixel data to both a CRT
screen and a DSTN panel at the same time is that horizon-
tal scan lines in both the upper and lower halves of a DSTN
panel screen must be written at the same time. This differs
from the order that pixel data is written to a CRT screen,
where the pixel data for one horizontal scan line at a time is
written to the screen, starting with the scan line at the top
of the screen and ending at the bottom of the screen.
Designs which incorporate the CS9211 are able to support
simultaneous display with a DSTN panel and CRT. The
CS9211 stores DSTN pixel data in the external frame buff-
ers, and then reorders the pixel data stream to include pixel
data for both the upper and lower halves of the screen
before sending the data out to the panel. The data in the
frame buffer has already been frame-rate-modulated
and/or dithered, if necessary, and packed as three bits per
pixel.
Simultaneous display is supported only with the panel and
CRT in the same mode and refresh rate. In this mode, the
refresh rate should be set as high as possible while main-
taining compatibility with established monitor timing stan-
dards.
Offset 404h-407h
Offset 420h-423h
Bit
31
4
3
2
1
0
Simultaneous Display
EDO_EDGE_SEL EDO Data Latch Edge Select: This bit controls which clock edge is used to latch data. When this bit is
HIGH_RESOL_
SDRAM_EDO
SDRAM_CLK
SDRAM_LD
EDO_LATE
_INVERT
MCLK
Name
Table 3-17. Memory Controller Programming Registers
Description
High Resolution MCLK: Selects the MCLK frequency in terms or the DOTCLK frequency.
This bit should be programmed as “0” for all the DSTN panels with resolutions up to 800x600, where the
memory clock is the same as the DOTCLK. This should be set to “1” for the 1024x768 DSTN panel to
run the memory clock at two-thirds the rate of the DOTCLK.
0 = Memory clock runs at the same frequency as DOTCLK.
1 = Memory clock runs at two-thirds the frequency of the DOTCLK.
EDO DRAM Late Latch Bit: When this bit is set, the data is latched into the CS9211, one clock after
the data arrives from the DRAM. Since SSTN and TFT panels do not use any frame buffer, this bit is
used only for DSTN panels. This bit is effective only if EDO RAM is used, as selected by bit 0 = 0.
0 = Latch the data with no delay.
1 = Latch the data with a delay of one clock.
set, the data from the DRAM is latched into the CS9211 on the negative edge of the memory clock.
Since SSTN and TFT panels do not use any frame buffer, this bit is used only for DSTN panels. This bit
is effective only if EDO RAM is used, as selected by bit 0 = 0.
0 = Latch on positive (rising) edge.
1 = Latch on negative (falling) edge.
SDRAM Load Bit: SDRAM Load Mode
SSTN and TFT panels do not use any frame buffer, this bit is used only for DSTN panels.
0 = Disable; 1 = Enable.
SDRAM Clock: Inverts the clock to the SDRAM interface. Since SSTN and TFT panels do not use any
frame buffer, this bit is used only for DSTN panels.
0 = Use inverted clock.
1 = Use non-inverted clock.
SDRAM or EDO: Selects external frame buffer memory type. Since SSTN and TFT panels do not use
any frame buffer, this bit is used only for DSTN panels. 0 = EDO; 1 = SDRAM.
(Continued)
Panel Timing Register 2 (R/W)
Memory Control Register
35
3.2.10 Maximum Frequency
The CS9211 will operate at a DOTCLK frequency of up to
65 MHz. There is no minimum frequency for the CS9211
device; however, many flat panels have signal timings that
require minimum frequencies. Refer to the flat panel dis-
play manufacturer’s specifications as appropriate.
3.2.11 Memory Controller
To support DSTN panels, the CS9211 memory interface
must be connected to a DRAM in either EDO (Extended
Data Out) or SDRAM format. This DRAM is used to store a
DSTN-formatted copy of the frame buffer. Pixel data is
received by the pixel port, formatted by the Frame Rate
Modulator and dither block, and then stored in the frame
buffer. The formatted pixel data is subsequently read from
the memory and used to refresh the DSTN panel. Table 3-
17 shows the registers associated with programming the
memory controller.
Register.
When enabled, this bit activates RAM refresh. Since
Reset Value = 1EF80008h
Reset Value = 00000000h
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