CS9211-VNG National Semiconductor, CS9211-VNG Datasheet - Page 34

• Manufacturer Part Number: CS9211-VNG
• Manufacturer: National Semiconductor

Specifications of CS9211-VNG

• Operating Temperature (max): 85C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

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Functional Description
Table 3-16 provides the mapping for the panel data bits as
inputs to the CRC.
Where:
and so on for the Upper Display from line 1 to line 240 of a
640x480 panel, and
and so on for the Lower Display from line 241 to line 480.
bit[0]
bit[1]
bit[2]
bit[3]
bit4]
bit[5]
bit[6]
bit[7]
bit[8]
bit[9]
bit[10]
bit[11]
bit[12]
bit[13]
bit[14]
bit[15]
bit[16]
bit[17]
bit[18]
bit[19]
bit[20]
bit[21]
bit[22]
bit[23]
(LD/UD)
Input
CRC
RU1/BU1/GU1 -> pixel 1
RU2/GU2/BU2 -> pixel 2
RL1/GL1/BL1 -> pixel 1
RL2/GL2/BL2 -> pixel 2
DSTN 24-Bit, Offset
404h[18:16] = 010
BU4
GU4
RU4
BU3
GU3
RU3
BU2
GU2
RU2
BU1
GU1
RU1
GL4
RL4
GL3
RL3
GL2
RL2
GL1
RL1
BL4
BL3
BL2
BL1
Table 3-16. Mapping of Panel Data as CRC Input
1st Input
(Continued)
to CRC
GU3
RU3
BU2
GU2
RU2
BU1
GU1
RU1
GL3
RL3
BL2
GL2
RL2
BL1
GL1
RL1
0
0
0
0
0
0
0
0
Offset 404h[18:16] = 001
DSTN 16-Bit,
2nd Input
to CRC
GU5
GU4
RU6
BU5
RU5
BU4
RU4
BU3
GL5
GL4
RL6
BL5
RL5
BL4
RL4
BL3
0
0
0
0
0
0
0
0
3rd Input
to CRC
BU8
GU8
RU8
BU7
GU7
RU7
GU6
34
BU6
BL8
GL8
RL8
BL7
GL7
RL7
BL6
GL6
0
0
0
0
0
0
0
0
Panel selection is done through the register bits at Offset
404h[18:16]. The selection of these bits generates the
desired SHFCLK from the pixel clock, based on the panel
type selected, and steers the internal pixel bus onto the
panel interface data pins (the LD and UD groups in Table 3-
4). All unused pins are driven with 0’s.
This panel data is sent to the CRC signature generator.
The CRC value varies for each panel configuration for a
fixed on-screen image.
1st Input
to CRC
G3
R3
G2
R2
G1
R1
B2
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Offset 404h[18:16] = 011
SSTN 8-Bit,
2nd Input
to CRC
R6
G5
R5
G4
B5
B4
R4
B3
3rd Input
to CRC
B8
G8
R8
B7
G7
R7
B6
G6
404h[18:16] = 010
TFT, Offset
G0
G1
G2
G3
G4
G5
R2
R5
B0
B1
B2
B3
B4
B5
R0
R1
R3
R4
0
0
0
0
0
0
Revision 2.1