CS9211-VNG National Semiconductor, CS9211-VNG Datasheet - Page 13

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CS9211-VNG

Manufacturer Part Number
CS9211-VNG
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of CS9211-VNG

Operating Temperature (max)
85C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS9211-VNG
Manufacturer:
NS/国半
Quantity:
20 000
Revision 2.1
Signal Definitions
2.2.5
2.2.6
2.2.7
Signal Name
RESET#
XTALIN
XTALOUT
GPIO0-GPIO7
Signal Name
TEST_SE
MBIST_EN
SCAN_EN
Signal Name
VDDIO
VSSIO
VDD
VSS
Reset, Crystal, and GPIO Pins
National Semiconductor Internal Test Pins
Power and Ground Pins
1, 17, 37,
2, 18, 38,
109, 126
91, 108,
Pin No.
Pin No.
Pin No.
89, 128
55, 72,
71, 90,
36, 73,
19, 54,
70:63
125
144
44
48
49
47
45
46
(Continued)
(Drive)
(Drive)
(Drive)
(4 mA)
Type
Type
Type
PWR
GND
PWR
GND
I/O
O
I
I
I
I
I
Description
System Reset Input
A system reset should be at least as long as one clock cycle of the slowest
of DOTCLK, XTALIN or SCLK. RESET# should be active for at least 1 ms.
Crystal Oscillator Connection
This pin is the crystal input for the on-chip reference oscillator or a CMOS
clock input from an external reference source. It should be 14.318 MHz.
Crystal Oscillator Connection
This pin is the crystal output for the on-chip reference oscillator. If an exter-
nal clock is used, leave this pin unconnected.
General Purpose Inputs/Outputs
Each GPIO pin can be configured independently as an input or output. For
further programming information refer to Section 3.2.13 “General Purpose
I/O Pins” on page 38.
Description
Reserved
This pin must be tied to ground for normal operation. It is a National
Semiconductor internal test mode pin only.
Reserved
This pin must be tied to ground for normal operation. It is a National
Semiconductor internal test mode pin only.
Reserved
This pin must be tied to ground for normal operation. It is a National
Semiconductor internal test mode pin only.
Description
Power Connection (total of 8 pins)
Power for the DRAM and system interface signals. These pins should be
supplied with 3.3V.
Ground Connection (total of 7 pins)
Ground connection.
Power Connection (total of 3 pins)
Power for the DRAM and system interface signals. These pins should be
supplied with 3.3V.
Ground Connection (total of 4 pins)
Ground connection.
13
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